Beyond Flat Netlist: Hierarchical Graph Representation Learning for Scalable Analysis of Sequential Circuits

Jingyi Zhou; Zhengyuan Shi; Jiaying Zhu; Ziyang Zheng; Qiang Xu

cs.LGAug 28, 2026

Beyond Flat Netlist: Hierarchical Graph Representation Learning for Scalable Analysis of Sequential Circuits

Authors: Jingyi Zhou, Zhengyuan Shi, Jiaying Zhu, Ziyang Zheng, Qiang Xu

Organizations: The Chinese University of Hong Kong, Hong Kong, China · Tsinghua University, Beijing, China

Abstract

Circuit Representation Learning (CRL) offers a powerful paradigm to guide and optimize core Electronic Design Automation (EDA) tasks, but its practical adoption is hindered by the immense scale of industrial netlists and a failure to explicitly model register-level temporal dynamics. To overcome these barriers, we introduce DeepSeq3, a novel hierarchical framework that abstracts circuits into a two-level representation: fine-grained combinational subgraphs partitioned by flip-flops (FFs), and a high-level Super-Node Graph (SNG) that models the register-transfer structure. A dual Graph Neural Network (GNN) architecture learns representations at both levels, capturing local Boolean logic and global state transitions. Crucially, we introduce a state-centric pre-training scheme that predicts the reachability between FF states, endowing the model with a deep understanding of temporal behavior. Demonstrated on large-scale benchmarks, DeepSeq3's approach yields superior scalability and richer representations, reducing bounded model checking (BMC) solving time by 18% while guaranteeing correctness.

Figures & tables

Figure 1. Overview of DeepSeq3 framework. (A) Subgraph partition and SNG construction. (B) Combinational logic subgraph learning with layer-wise GNN. (C) SNG representation learning framework and applied to various downstream tasks.

Figure 2. An example of SNG construction

Model	Stage 1: Combinational Subgraph				Stage 2: Register-Level Evaluation
	$\mathcal{L}_{1}$		$\mathcal{L}_{0}$		IR			OT		Time (s)
	R 2	MAE	R 2	MAE	Recall	F1	Accuracy	R	MAE
GCN ( Kipf and Welling, 2017 )	0.7996	0.0785	0.7910	0.0902	-	-	-	-	-	-
GAT ( Veličković et al., 2018 )	0.6073	0.1117	0.5573	0.1156	-	-	-	-	-	-
GraphSAGE ( Hamilton et al., 2017 )	0.9552	0.0367	0.9565	0.0403	-	-	-	-	-	-	-
HOGA-3 ( Deng et al., 2024 )	0.6066	0.1179	0.6038	0.1186	-	-	-	-	-	-

Table 1. Performance comparison on model pre-training tasks.

Circuit	Nodes	Power	DeepSeq2		DeepSeq3
Circuit	Nodes	Power	Power	Error	Power	Error
ptc	2,024	0.0677	0.0710	4.89%	0.0717	5.92%
noc_router	5,246	0.2184	0.2288	4.76%	0.2196	0.55%
mem_ctrl1	10,733	0.3148	0.3800	20.70%	0.3641	15.66%
ac97_ctrl	14,004	0.5512	0.5391	2.24%	0.5517	0.09%
pll	18,208	0.7787	0.7428	4.61%	0.7735	0.67%

Table 2. Predicted Power Comparison

Figure 4. Solving time comparison on easy instances

Circuit	Nodes	Raw BMC ( Brayton and Mishchenko, 2010 )	Guided BMC
Circuit	Nodes	Time (s)	SolveTime (s)	InferTime (s)	Total (s)
eijks208o	172	15.63	11.97	0.74(0.5+0.24)	12.71
pdtvispeterson	712	22.92	18.27	1.01(0.75+0.26)	19.28
pdtvisgigamax0	1,107	13.99	14.61	2.25(2.00+0.25)	16.86
float_reg_b1_1071	2,066	11.02	10.93	1.30(1+0.30)	12.23
float8	10,590	71.05	61.37	7.81(7.5+0.31)	69.18

Table 3. Solving time comparison on hard instances

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Graph Neural Networks (GNNs) show strong promise for circuit analysis, but scaling to modern large-scale circuit graphs is limited by GPU memory and training cost, especially for deep models. We revisit deep GNNs for circuit graphs and show that, when trainable, they significantly outperform shallow architectures, motivating an efficient, domain-specific training framework. We propose Grouped-Sparse-Reversible GNN (GSR-GNN), which enables training GNNs with up to hundreds of layers while reducing both compute and memory overhead. GSR-GNN integrates reversible residual modules with a group-wise sparse nonlinear operator that compresses node embeddings without sacrificing task-relevant information, and employs an optimized execution pipeline to eliminate fragmented activation storage and reduce data movement. On sampled circuit graphs, GSR-GNN achieves up to 87.2% peak memory reduction and over 30

\times

training speedup with negligible degradation in correlation-based quality metrics, making deep GNNs practical for large-scale EDA workloads.

Abstract

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