PRISM-UDE: Physics-Regularized Iterative Symbolic Modeling of 3nm FinFETs via Universal Differential Equation

Pranavanath Balamurali; Prathamesh Dinesh Joshi; Raj Abhijit Dandekar; Rajat Dandekar; Sreedath Panat

cs.ETAug 14, 2026

PRISM-UDE: Physics-Regularized Iterative Symbolic Modeling of 3nm FinFETs via Universal Differential Equation

Authors: Pranavanath Balamurali, Prathamesh Dinesh Joshi, Raj Abhijit Dandekar, Rajat Dandekar, Sreedath Panat

Organizations: The University of Texas at Austin · Vizuara AI Labs

Abstract

Compact transistor models are the mathematical backbone of circuit simulation. However, at advanced nodes such as 3nm, transport physics becomes too complex for traditional hand-derived equations to capture accurately. Purely data-driven neural surrogates, on the other hand, are numerically unstable inside circuit solvers and offer no physical insight into their own predictions. We introduce PRISM-UDE (Physics-Regularized Iterative Symbolic Modeling via Universal Differential Equations), a framework that embeds a small neural network inside a physics-based transistor model, using the network only to learn the transport behavior that the analytical baseline misses, rather than replacing the physics altogether. Once trained, this neural correction is distilled into a single, interpretable closed-form expression via symbolic regression, making the final model fully analytical and simulator-ready. Applied to a 3nm FinFET benchmark dataset, PRISM-UDE reduces prediction error more than sixfold (70.33% to 11.01%) relative to the standard physics-only baseline. The distilled expression preserves this accuracy almost exactly while eliminating the neural network entirely. We further validate the extracted expression directly inside a SPICE circuit simulator, confirming stable, physically consistent behavior under both static bias sweeps and dynamic switching conditions.

Figures & tables

Field Entity	Physical / Modeling Description	Data Representation & Units
PDK	Anonymized Process Design Kit Identification Tag	String ( "N3A" )
Node	Target lithography process minimum feature boundary	Integer ( $3$ nm)
Device	Multi-gate device structural designation	String ( "NMOS" )
Corner	Process variation boundaries	String ( "TT" )
Temp	Environmental validation temperature matrix	Integer ( $-40^{\circ}\text{C}$ to $125^{\circ}\text{C}$ )
L	Effective drawn physical gate length	Integer ( $15$ nm)

Table 1: Structural Fields and Feature Dimensions of the Isolated MESD N3A FinFET Partition

Figure 1: End-to-end PRISM-UDE pipeline: a physics-grounded transport scaffold constrains a neural residual correction, which is jointly optimized in two stages, distilled into a closed-form expression via symbolic regression, and validated directly inside a SPICE circuit simulator.

Parameter	Physical Description	Extracted Value	Units
$\mu_{00}$	Baseline Low-Field Intrinsic Electron Mobility	$0.01000$	$\text{m}^{2}/\text{V}\cdot\text{s}$
$V_{th0}$	Intrinsic Zero-Bias Flatband Threshold Voltage	$0.18859$	V
$m$	Subthreshold Ideality Factor (Gate Control Swing)	$1.19241$	$-$
DIBL	Drain-Induced Barrier Lowering Coefficient	$0.10314$	$\text{V}/\text{V}$
$C_{ox}$	Effective Gate Dielectric Oxide Capacitance	$0.03365$	$\text{F}/\text{m}^{2}$

Table 2: Extracted Primary Physical Baseline Parameters (Stage 1 PSO)

	MESD Training Partition		Held-Out Evaluation Partition
Model Configuration	RMSE (A)	MRE (%)	RMSE (A)	MRE (%)
CT Baseline Scaffolding (Stage 1)	$8.44\times 10^{-5}$	$73.82\%$	$6.94\times 10^{-5}$	$70.33\%$
Neural Hybrid UDE (Stage 2)	$1.93\times 10^{-5}$	$10.45\%$	$1.73\times 10^{-5}$	$11.01\%$
Symbolic Model (Deployed SPICE Expression)	$\mathbf{2.07\times 10^{-5}}$	$\mathbf{11.83\%}$	$\mathbf{1.91\times 10^{-5}}$	$\mathbf{12.38\%}$

Table 3: Global Model Performance Metrics across Optimization Boundaries

Figure 2: Multi-decade training loss descent (a) and global prediction parity (b) for the neural UDE optimization. Panel (a) tracks the log-space loss

\mathcal{L}_{\text{log}}

over training epochs. Panel (b) compares predicted versus reference

I_{ds}

across the full training sweep, with the diagonal indicating good agreement.

Figure 3: Multi-panel validation matrix profiling

I_{ds}

–

V_{gs}

transfer characteristics across independent drain-to-source biases (

V_{ds}=0.1

0.2

0.3

0.4

0.6

V) and thermal operational boundaries (

T=-40^{\circ}\text{C},0^{\circ}\text{C},25^{\circ}\text{C},125^{\circ}\text{C}

). Solid blue lines track the neural UDE model prior to symbolic regression, solid black lines represent the MESD reference ground truth, and dashed red lines mark the unaugmented physical baseline scaffolding. The tight alignment between the neural UDE and the reference data across all coordinates demonstrates accurate multi-variable interpolation and physical scaling without artifacts at the operational boundaries of the MESD envelope. The corresponding accuracy of the distilled symbolic expression is reported separately in Table 3 (configuration A8 ).

Operational Evaluation Slice	Structural Parameter Condition	MSLE
Extreme Geometric Gate Limit	$N_{fin}=16$	$3.7637\times 10^{-3}$
Nominal Room Thermal State	$T=25^{\circ}\text{C}$	$4.5794\times 10^{-3}$
Extended Thermal Boundary	$T=125^{\circ}\text{C}$	$5.1208\times 10^{-3}$

Table 4: Detailed Log-Domain Tracking Error Breakdown (

\text{MSLE}_{\text{UDE}}

)

Figure 4: Thermal generalization sweeps profiling subthreshold performance and threshold voltage shifting across a operating envelope (

0^{\circ}\text{C}

125^{\circ}\text{C}

) at: (a)

0^{\circ}\text{C}

, (b)

25^{\circ}\text{C}

, (c)

85^{\circ}\text{C}

, and (d)

125^{\circ}\text{C}

. Solid blue lines track our neural UDE model prior to symbolic regression, solid black lines represent the reference ground truth, and dashed red lines mark the unaugmented Caughey–Thomas baseline. The plots demonstrate that the physics-guided structure accurately captures subthreshold swing degradation and weak-inversion leakage across all thermal states where the baseline fails.

Modeling Framework	Mean SS $\pm$ Std. Dev. (mV/dec)	Absolute Mean Discrepancy
MESD Reference Ground Truth	$79.6\pm 15.5$	Base Standard
Extracted Baseline Scaffolding	$76.9\pm 14.3$	$-2.7$ mV/dec
Synthesized UDE Symbolic Model (Ours)	$\mathbf{81.0\pm 14.4}$	$\mathbf{+1.4}$ mV/dec

Table 5: Statistical Distribution of Subthreshold Swing (SS)

ID	Configuration Variant	Core Architectural/Data Modification	RMSE (A)	MRE (%)	Max $I_{\text{ghost}}$ at $V_{\text{ds}}=0$ V (A)
A1	Physical Baseline	Baseline Caughey–Thomas drift-diffusion scaffolding only	$6.94\times 10^{-5}$	$70.33\%$	$0.00$ (Preserved)
A2	Pure Black-Box MLP	Unconstrained 2-hidden layer neural network surrogate	$5.54\times 10^{-3}$	$2.06\times 10^{7}\%$	$3.86\times 10^{-2}$ ( VIOLATED )
A3	Linear Loss Ablation	Identical UDE model optimized via standard linear MSE loss	$6.40\times 10^{-5}$	$159.91\%$	$0.00$ (Preserved)
A4	PRISM-UDE (Ours)	Continuous neural transport operator embedded in scaffold (64 hidden neurons)	$\mathbf{1.73\times 10^{-5}}$	$\mathbf{11.01\%}$	$\mathbf{0.00}$ (Preserved)
Compression, Training-Set Reduction, and Thermal-Extreme Evaluation
A5	Hidden Width = 8	Reduced capacity neural operator (8 hidden neurons)	$2.60\times 10^{-5}$	$14.11\%$	$0.00$ (Preserved)

Table 6: Complete Structural Ablation and Architectural Sensitivity Performance Matrix (Held-Out Evaluation Partition)

Complexity ( $\mathcal{C}$ )	Residual Loss	Recovered Closed-Form Expression
1	$1.607\times 10^{-5}$	$y=\mu_{CT}$
2	$2.231\times 10^{-6}$	$y=\ln(0.99997)$
3	$1.808\times 10^{-6}$	$y=-0.20810\cdot\mu_{CT}$
5	$1.442\times 10^{-6}$	$y=\mu_{CT}\cdot(0.96342-\text{TRatio})$
6	$1.358\times 10^{-6}$	$y=(V_{ds}-\ln(\text{TRatio}))\cdot\mu_{CT}$
9	$9.192\times 10^{-7}$	$y=(V_{ds}-(\text{TRatio}-0.78803))\cdot(\mu_{CT}/\text{TRatio})$

Table 7: Pareto Frontier for Extracted Mobility Field Correction

Figure 5: Model selection and compression trade-off verified via the Pareto regression frontier. The chart maps algebraic complexity against symbolic regression residual loss, highlighting the selected optimal expression at a complexity score of 15. The frontier illustrates that the framework compresses the neural network into a compact functional form with a negligible accuracy penalty.

Constant	Extracted Value	Dimension	Physical Significance & Governance
$\alpha_{0}$	$10^{-6}$	$\text{m}^{4}\cdot\text{V}^{-2}\cdot\text{s}^{-2}$	Smoothness regularizer for $\mathcal{C}^{\infty}$ continuity at zero-bias conditions.
$\alpha_{1}$	$1.0000$	Dimensionless	High-field horizontal drift coupling coefficient.
$\alpha_{2}$	$0.06499$	Dimensionless	Quantum subband splitting and vertical field degradation parameter.
$\alpha_{3}$	$0.07219$	Dimensionless	Low-bias gate-field screening saturation parameter.

Table 8: Extracted Constants and Physical Governance for the Discovered Transport Model

Figure 6: Physical validity verification of the distilled symbolic model via SPICE DC family of curves (

I_{D}

–

V_{DS}

). The output characteristics are generated by implementing the recovered closed-form algebraic expression as a continuous behavioral source. Bias values up to

0.7

V lie within the MESD N3A training envelope; the

0.7

–

1.2

V region is extrapolation beyond the fitted domain and is included to test numerical robustness rather than quantitative accuracy. The model tracks the linear conduction region, exhibits a saturation knee that shifts with gate bias, and preserves exact zero-bias boundaries. The smooth, monotonic current ordering confirms that the physics-guided structure yields stable behavior across all simulated bias combinations.

Figure 7: Dynamic stability and numerical robustness verification of the distilled symbolic model via SPICE transient simulation. Left: The corresponding model-predicted channel current response (

I_{D}

). Right: The input waveform executing rapid square-wave gate voltage switching (

V_{GS}

) between 0 V and 1.2 V, the upper level lying beyond the

0.7

V MESD training envelope. The clean current envelopes and absence of numerical oscillation under steep step-function inputs demonstrate that the distilled algebraic expression maintains numerical continuity and solver convergence, verifying its feasibility for stable transport-model prototyping inside circuit simulation engines. Current magnitudes above

0.7

V are extrapolated and are not validated against reference data.

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NN-Based Transistor Modeling for Ultra-Fast SPICE Simulation and Standard Cell Library Characterization

Rodion Novkin, Hussam Amrouch

Technical University of Munich; TUM School of Computation, Information and Technology; Chair of AI Processor Design; Munich Institute of Robotics and Machine Intelligence, Munich, Germany

Neural Surrogate Modeling Electronic Design Automation

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Neural network (NN)-based transistor models have proven to be a promising solution to accelerate device modeling. Although these models demonstrated remarkable speedup in circuit simulations, they were not rigorously tested in complex tasks within standard EDA tool flows for chip design, which require very high transistor model precision to provide accurate results and converge properly. To investigate their full potential and promise, we develop NN-based transistor models that accurately predict the drain current and various charges for a 3nm nanosheet, and employ the models for a standard cell library characterization. This enables us to evaluate the accuracy and speedup under a very wide range of SPICE simulations, benchmarking our models against an industry-standard implementation. Since standard cell library characterization involves thousands of SPICE simulations, it serves as a great benchmark for transistor model quality and consistency. To further evaluate model accuracy, we also perform analog- and digital-level simulations for various complex circuits. Our experiments reveal that NN-based models are a valid alternative to existing transistor compact models, capable of producing accurate delay and power estimates with a much higher speed and convergence time compared to the conventional Verilog-A-based industry-standard (BSIM-CMG) transistor compact model. Our NNs achieve sub-0.11% and 0.76% errors for delay and total power evaluation on a wide range of circuits, while taking up to 8 times less time during the standard cell library characterization. Additionally, we provide comprehensive information and guidance on NN accuracy, unveiling the relationship between NN size and its effect on circuit simulation precision.

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