ENAS: An Efficient Hardware-Aware Neural Architecture Search Framework for TinyML on Resource-Constrained Microcontrollers

Mohd Moin Khan; Naman Srivastava; Pandarasamy Arjunan

cs.LGAug 10, 2026

ENAS: An Efficient Hardware-Aware Neural Architecture Search Framework for TinyML on Resource-Constrained Microcontrollers

Authors: Mohd Moin Khan, Naman Srivastava, Pandarasamy Arjunan

Organizations: Indian Institute of Science (IISc), Bengaluru 560012, India

Abstract

We present ENAS, a hardware-aware Neural Architecture Search (NAS) framework that combines a static feasibility check, a cell-based search space supporting standard, depthwise-separable, and bottleneck blocks with optional skip connections, and a three-stage hybrid search strategy (random $\rightarrow$ top- $K$ $\rightarrow$ mutation) with persistent cross-run caching. Unlike many existing NAS frameworks that rely on GPU acceleration, ENAS is designed to operate efficiently without requiring GPUs, making it suitable for resource-constrained development environments. We evaluate ENAS on two TinyML benchmarks, Visual Wake Words and Melanoma Cancer, across eight microcontrollers with memory footprints ranging from 20,KB to 1,MB SRAM and nine input image resolutions. Our experimental results show that ENAS achieves mean search-time speedups of $2.41{\times}$ and $1.70{\times}$ on the Visual Wake Words and Melanoma Cancer datasets, respectively, while maintaining competitive test accuracy compared with the recent NanoNAS framework. A measured resource analysis further shows that ENAS-selected models use substantially lower peak activation RAM, the binding constraint for microcontroller deployment at matched accuracy. Additionally, ENAS achieves $79.4\%$ test accuracy on an STM32H743-based microcontroller, outperforming the greedy CPU-only baseline by $2.6$ percentage points. We release the ENAS framework as open-source at: https://github.com/EdgeIntelligenceLab/ENAS

Figures & tables

Panel of Figure 1 — Figure 1: ENAS pipeline (left) and cell-based architecture template (right). Phase 0 eliminates infeasible candidates analytically. Phase 1 evaluates 70 candidates (30 random + 40 mutants (5 per top- $K$ survivor)) using short proxy training. Each cell is independently configured across six dimensions: block type, kernel size, stride, skip connection, activation, and expansion ratio.

Figure 2: Analytical activation-memory boundary. Peak RAM scales with $H\cdot W\cdot k\cdot 4$ bytes, accurately predicting the infeasible regions later detected by NanoNAS during its measured TFLite deployment check.

Platform	RAM	Flash	MACC
STM32L010RBT6	20 KB	128 KB	0.75 M
NUCLEO-L010RB	20 KB	64 KB	0.75 M
Arduino Nano33IoT	32 KB	256 KB	1.20 M
NUCLEO-L412KB	64 KB	128 KB	3.20 M
Raspberry Pi Pico	264 KB	2 MB	3.00 M
Arduino Nano33BLE	256 KB	1 MB	4.00 M

Table 1: Target MCU platforms.

Metric	VWW		Cancer
	NanoNAS	ENAS	NanoNAS	ENAS
Mean acc. (%)	$72.68{\scriptstyle\,\pm\,2.58}$	$71.89{\scriptstyle\,\pm\,3.33}$	$89.44{\scriptstyle\,\pm\,1.26}$	$88.13{\scriptstyle\,\pm\,1.52}$
Median acc. (%)	72.71	72.24	89.77	88.23
Mean search (min)	$102.2{\scriptstyle\,\pm\,44.6}$	$42.4{\scriptstyle\,\pm\,21.2}$	$10.3{\scriptstyle\,\pm\,3.8}$	$6.1{\scriptstyle\,\pm\,2.6}$
Speedup	2.41 $\times$		1.70 $\times$
Acc. $p$ -value	$0.118$ (n.s.)		$3.4\times 10^{-6}$

Table 2: Aggregate results across all 53 feasible (hardware, resolution) cells per dataset. Each cell statistic is the mean over 3 runs; aggregate values are mean

\pm

std over the 53 cell means.

p

-values are from two-sided Wilcoxon signed-rank tests comparing ENAS and NanoNAS for each dataset.

Dataset	Method	RAM (KB)	Flash (KB)	MACC (M)
VWW	NanoNAS	$40.4{\scriptstyle\,\pm\,28.6}$	$14.0{\scriptstyle\,\pm\,4.6}$	$1.77{\scriptstyle\,\pm\,1.49}$
VWW	ENAS	$12.1{\scriptstyle\,\pm\,5.5}$	$53.8{\scriptstyle\,\pm\,37.8}$	$2.56{\scriptstyle\,\pm\,2.44}$
Cancer	NanoNAS	$37.0{\scriptstyle\,\pm\,27.3}$	$9.4{\scriptstyle\,\pm\,2.4}$	$0.86{\scriptstyle\,\pm\,0.86}$
Cancer	ENAS	$7.6{\scriptstyle\,\pm\,4.1}$	$50.7{\scriptstyle\,\pm\,42.0}$	$1.85{\scriptstyle\,\pm\,1.72}$
Ratio (all, VWW / Cancer)		0.30 / 0.21	3.84 / 5.40	1.44 / 2.15
Ratio (matched acc.)		0.38 / 0.38	2.85 / 5.73	1.39 / 3.94

Table 3: Measured resource footprint of selected models, mean

\pm

std over the 53 feasible cells (RAM and Flash measured with stm32tflm ; MACC analytical). The final two rows give the ENAS/NanoNAS ratio over all cells and restricted to matched-accuracy cells (

|\Delta\text{acc}|\leq 1

pp).

		Visual Wake Words						Melanoma Cancer
		Accuracy (%)			Search (min)			Accuracy (%)			Search (min)
Input	$N$	NanoNAS	ENAS	$\Delta$	Nano	ENAS	Sp.	NanoNAS	ENAS	$\Delta$	Nano	ENAS	Sp.
$32^{2}$	8	$69.6{\scriptstyle\,\pm\,3.1}$	$71.6{\scriptstyle\,\pm\,1.9}$	$+2.05$	58	39	1.50	$89.9{\scriptstyle\,\pm\,1.1}$	$89.2{\scriptstyle\,\pm\,1.3}$	$-0.69$	9	6	1.49
$48^{2}$	8	$71.4{\scriptstyle\,\pm\,1.2}$	$72.1{\scriptstyle\,\pm\,4.3}$	$+0.66$	82	37	2.25	$90.0{\scriptstyle\,\pm\,1.0}$	$88.4{\scriptstyle\,\pm\,1.5}$	$-1.57$	10	5	1.82
$50^{2}$	8	$72.6{\scriptstyle\,\pm\,1.3}$	$70.9{\scriptstyle\,\pm\,3.8}$	$-1.77$	103	37	2.80	$89.6{\scriptstyle\,\pm\,1.0}$	$88.4{\scriptstyle\,\pm\,1.0}$	$-1.22$	10	5	1.90
$64^{2}$	6	$72.9{\scriptstyle\,\pm\,1.4}$	$72.6{\scriptstyle\,\pm\,3.4}$	$-0.24$	108	41	2.62	$89.1{\scriptstyle\,\pm\,1.8}$	$88.5{\scriptstyle\,\pm\,1.1}$	$-0.58$	10	6	1.64

Table 5: Per-resolution accuracy (%, mean

\pm

std over the

N

feasible cells) and search time (min) across all feasible hardware platforms.

\Delta=\text{ENAS}-\text{NanoNAS}

in percentage points; speedup

=\text{NanoNAS}/\text{ENAS}

. The mean speedups (

2.41{\times}

on VWW,

1.70{\times}

on Cancer) hold uniformly across resolutions, while accuracy varies by tier and input size.

Figure 3: Accuracy versus search-time Pareto across all 212 cells. ENAS (teal squares) cluster at lower search times; NanoNAS (dark circles) spans a wider accuracy range. Cross-dataset stratification is visible: Cancer at top ( $\sim$ 89%), VWW at bottom ( $\sim$ 73%).

HW	RAM	NanoNAS		ENAS		Speed
	(KB)	acc	Px	acc	Px	up
L010RBT6	20	$72.7{\scriptstyle\,\pm\,1.4}$	$50$	$70.7{\scriptstyle\,\pm\,3.4}$	$32$	2.44 $\times$
L010RB	20	$72.0{\scriptstyle\,\pm\,1.3}$	$50$	$68.3{\scriptstyle\,\pm\,3.1}$	$32$	2.79 $\times$
IoT	32	$72.7{\scriptstyle\,\pm\,1.4}$	$32$	$70.4{\scriptstyle\,\pm\,3.6}$	$32$	2.84 $\times$
L412	64	$75.5{\scriptstyle\,\pm\,0.6}$	$80$	$74.0{\scriptstyle\,\pm\,3.5}$	$48$	1.65 $\times$
Pico	264	$75.9{\scriptstyle\,\pm\,0.5}$	$96$	$74.3{\scriptstyle\,\pm\,1.9}$	$50$	3.48 $\times$

Table 6: Per-hardware best TFLite accuracy on VWW (mean

\pm

std over 3 runs at the best-accuracy resolution). “Px” is that resolution; “Speed” is the ENAS search-time advantage at the ENAS-best configuration.

Figure 4: Per-cell deltas (ENAS vs. NanoNAS) across both datasets. Top row: $\Delta$ TFLite accuracy in percentage points (green $=$ ENAS better). Bottom row: $\Delta$ search time in minutes (green $=$ ENAS faster). The H743 row in panel (a) shows the strongest ENAS dominance ( $+10.5$ pp at $32{\times}32$ , $+10.6$ pp at $80{\times}80$ ); the search-time panels are almost uniformly green. Grey hatched cells are RAM-infeasible.

Variant	Mean $50{\times}50$	Mean $64{\times}64$
ENAS-strategy (2-D space)	70.2	71.5
ENAS, $E_{p}{=}1$ , $w_{\text{acc}}{=}0.65$	68.8	70.5
+ $E_{p}{=}3$	70.6	72.7
+ $w_{\text{acc}}{=}0.80$	71.1	73.2
+ two-phase Stage 2	71.4	73.5
+ warm seed (full ENAS)	71.7	73.7

Table 7: Ablation of design and calibration choices (mean VWW TFLite accuracy, %, at the two focused input sizes; single-configuration design progression). The proxy-epoch and scoring-weight choices together account for

2.4

pp; the two-phase ranking and warm seed each add a further

0.3

pp.

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Efficient Neural Network Inference Tiny ML Hardware-Aware NAS Convolutional Neural Networks Edge ML Lightweight CNNs+1

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Hardware-aware neural architecture search (HW-NAS) allows the integration of Convolutional Neural Networks (CNNs) in microcontrollers devices by automatically designing neural architectures that can fit prearranged hardware constraints. However, state-of-the-art HW-NAS target high-performance microcontrollers, whose power consumption does not meet sensing nodes requirements. This work presents a HW-NAS generating tiny CNNs that can run on ultra-low-power microcontrollers, featuring a lightweight search procedure enabling its execution even on embedded devices. Empirical results on three well-known benchmarks for tiny computer vision proved that the proposed HW-NAS was able to generate tiny CNNs while preserving state-of-the-art classification accuracy.

Abstract

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