A Voltage-controlled MTJ-CMOS Neuron Emulating Tunable Izhikevich-Inspired Dynamics
Authors: Kayode Oluwaseyi Adebunmi, Jordan Athas, Allison Fleming, Hamed Poursiami, Giorgio A. Ascoli, Maryam Parsa, Pedram Khalili Amiri, Akhilesh R Jaiswal
Organizations: Electrical and Computer Engineering, University of Wisconsin–Madison, Madison, 500 Lincoln Dr, Madison, 53706, Wisconsin, USA. · Electrical and Computer Engineering, Northwestern University, Evanston, IL, City, 60208, State, USA. · Electrical and Computer Engineering, George Mason University, 4400 University Dr, Fairfax, Virginia, 22030, Virginia, USA.
Biological neurons exhibit diverse firing dynamics that enable adaptive and stimulus-dependent signalling, yet reproducing these dynamics in hardware has remained an enduring challenge. In this work, we present an Izhikevich- inspired reconfigurable neuron that co-designs voltage-controlled magnetic tunnel junction (V-MTJ) dynamics with CMOS circuitry. The proposed architecture combines V-MTJ excitability dynamics, enabled by a tunable energy landscape, with CMOS recovery dynamics to generate five distinct neuronal firing pat- terns with different spiking, bursting and response characteristics. Our results, based on measured V-MTJ characteristics and circuit simulations using com- mercial GlobalFoundries 22-nm FD-SOI CMOS technology, show an average energy consumption of 145.44 fJ per spike. Algorithmic simulations further show that these firing dynamics reduce inference spike activity by up to 88.6% while maintaining baseline classification accuracy. These results highlight the potential of V-MTJ/CMOS reconfigurable neurons to reduce computational activity and enable compact, energy-efficient brain-inspired computing systems.
Figure 2: V-MTJ characterization: (a) Device stack. (b) Time trace of device resistance fluctuating due to thermal stochasticity. (c) Magnetization dwell time as function of voltage. (d) Probability of finding the device in the P or AP state at a given time as a function of external magnetic-field bias.
Figure 3: V-MTJ/CMOS neuron architectural blocks: (a) V-MTJ excitability circuit for generating the excitation window through voltage-controlled MTJ switching dynamics. (b) Membrane dynamics circuit for membrane charging, threshold integration, and spike generation. (c) Spike-triggered increment circuit for recovery accumulation and firing adaptation. (d) Recovery circuit for implementing recovery-controlled leakage and temporal adaptation dynamics.
Figure 4: Simulated firing behaviors of the proposed V-MTJ/CMOS neuron, demonstrating its ability to emulate diverse biologically inspired firing patterns. (a) Tonic bursting, characterized by repetitive burst events. (b) Tonic spiking, exhibiting sustained periodic spike generation. (c) Phasic bursting, producing a single burst event. (d) Phasic spiking, producing a single spike. (e) Spike latency, characterized by a delayed spike.
Figure 5: Software emulation of multi-pattern neural dynamics (a) Simulated tonic-bursting response showing repetitive clusters of high-frequency spikes interspersed with silent refractory periods under a constant input stimulus ( Iin=1.0 ). (b) Simulated phasic-bursting response exhibiting a transient high-frequency burst at stimulus onset followed by sustained quiescence.
Classification Accuracy (%)
Spikes per Inference (Mean ± SD)
Dataset
LIF
Tonic Burst
Phasic Burst
LIF
Tonic Burst
Phasic Burst
MNIST
97.80
97.59
97.59
9,326 ± 3,581
5,177 ± 568*
3,449 ± 147 *
Fashion-MNIST
85.21
85.73
86.76
42,861 ± 12,948
13,707 ± 3,708*
4,916 ± 647 *
Breast Cancer
97.39
97.39
97.39
765 ± 423
444 ± 81*
328 ± 16 *
IRIS
96.77
96.77
96.77
2,123 ± 332
750 ± 56*
431 ± 8 *
Table 1: Comparison of classification accuracy and spike activity across neuron models. SNNs utilizing bursting dynamics (Fig. 5 ) drastically reduce the network spike count required per inference compared to the LIF baseline, without suffering notable degradation in task performance. ( ∗p<0.001 versus LIF baseline, Welch’s t-test.)
Spiking neural networks encode information in spike timing and offer a pathway toward energy efficient artificial intelligence. However, a key challenge in spiking neural networks is realizing nonlinear and expressive computation in compact, energy-efficient hardware without relying on additional circuit complexity. In this work, we examine nonlinear computation in a CMOS+X spiking neuron implemented with a magnetic tunnel junction connected in series with an NMOS transistor. Circuit simulations of a multilayer network solving the XOR classification problem show that three intrinsic neuronal properties enable nonlinear behavior: threshold activation, response latency, and absolute refraction. Threshold activation determines which neurons participate in computation, response latency shifts spike timing, and absolute refraction suppresses subsequent spikes. These results show that magnetization dynamics of MTJ devices can support nonlinear computation in compact neuromorphic hardware.
Steven Louis, Hannah Bradley, Artem Litvinenko +3
Department of Electrical and Computer Engineering · Oakland University, Rochester, MI USA · Department of Physics
Signed spiking neurons carry richer information than standard spiking neurons. This work proposes a compact magnetic tunnel junction (MTJ)-based neuron for signed leaky integrate-and-fire (LIF) operation. With orthogonal easy axes in the free and pinned layers, the device enables bipolar spike generation and maps magnetic-moment dynamics to signed LIF membrane-potential evolution. Landau--Lifshitz--Gilbert simulations show that proper free-layer dimensions allow the device response to follow a signed LIF equation. A representative design of 10 nm x 45 nm x 50 nm corresponds to an aspect ratio of about 2:9:10. Network evaluations using the fitted device-neuron model achieve 91.06% on CIFAR-10 and 77.40% on CIFAR10-DVS, retaining most of the accuracy of ideal signed LIF neurons.
Huannan Zheng, Jingli Liu, Kezhou Yang
Function Hub, The Hong Kong University of Science and Technology (Guangzhou), Guangzhou, 51000, China
The hippocampus, a key brain region for learning and memory, exhibits rich structural diversity, sparse communication, and robust dynamics with incredible energy efficiency. It offers promising insights for novel computing capabilities, particularly when co-designed with emerging hardware technologies. In this work, we draw inspiration from the rodent CA3 hippocampal subregion to develop the first spiking neural network with neuronal diversity and biologically-realistic resting state dynamics demonstrated on memristor hardware. We propose a network downscaling methodology utilizing a 4-prong objective function and demonstrate a small-scale CA3-inspired network with 179 Izhikevich-modeled neurons, 3 neuronal types and 17,996 synapses with similar resting-state dynamics as the orders-of-magnitude larger full-scale network. The small-scale network is mapped to an FPGA/memristor platform using a greedy algorithm and 18,316 memristors. Benefiting from memristor noise, the hardware implementation shows continuous periodic behavior, outperforming simulated hardware. This work showcases the potential of biologically-realistic algorithms on emerging hardware for neuromorphic computing.
Joseph A. Kilgore, Jeffrey D. Kopsick, Zahin Ahmed +2
Department of Electrical and Computer Engineering, George Washington University, Washington, 20052, USA · Center for Neural Informatics, Structures, & Plasticity, George Mason University, Fairfax, 22030, USA