A Voltage-controlled MTJ-CMOS Neuron Emulating Tunable Izhikevich-Inspired Dynamics

Kayode Oluwaseyi Adebunmi; Jordan Athas; Allison Fleming; Hamed Poursiami; Giorgio A. Ascoli; Maryam Parsa; Pedram Khalili Amiri; Akhilesh R Jaiswal

cs.ETSep 25, 2026

A Voltage-controlled MTJ-CMOS Neuron Emulating Tunable Izhikevich-Inspired Dynamics

Authors: Kayode Oluwaseyi Adebunmi, Jordan Athas, Allison Fleming, Hamed Poursiami, Giorgio A. Ascoli, Maryam Parsa, Pedram Khalili Amiri, Akhilesh R Jaiswal

Organizations: Electrical and Computer Engineering, University of Wisconsin–Madison, Madison, 500 Lincoln Dr, Madison, 53706, Wisconsin, USA. · Electrical and Computer Engineering, Northwestern University, Evanston, IL, City, 60208, State, USA. · Electrical and Computer Engineering, George Mason University, 4400 University Dr, Fairfax, Virginia, 22030, Virginia, USA.

Abstract

Biological neurons exhibit diverse firing dynamics that enable adaptive and stimulus-dependent signalling, yet reproducing these dynamics in hardware has remained an enduring challenge. In this work, we present an Izhikevich- inspired reconfigurable neuron that co-designs voltage-controlled magnetic tunnel junction (V-MTJ) dynamics with CMOS circuitry. The proposed architecture combines V-MTJ excitability dynamics, enabled by a tunable energy landscape, with CMOS recovery dynamics to generate five distinct neuronal firing pat- terns with different spiking, bursting and response characteristics. Our results, based on measured V-MTJ characteristics and circuit simulations using com- mercial GlobalFoundries 22-nm FD-SOI CMOS technology, show an average energy consumption of 145.44 fJ per spike. Algorithmic simulations further show that these firing dynamics reduce inference spike activity by up to 88.6% while maintaining baseline classification accuracy. These results highlight the potential of V-MTJ/CMOS reconfigurable neurons to reduce computational activity and enable compact, energy-efficient brain-inspired computing systems.

Figures & tables

Figure 1: V-MTJ/CMOS neuron architectural blocks: (a) Biological brain. (b) 3D-integrated V-MTJ/CMOS neuron technology. (c) Circuit implementation.

Figure 2: V-MTJ characterization: (a) Device stack. (b) Time trace of device resistance fluctuating due to thermal stochasticity. (c) Magnetization dwell time as function of voltage. (d) Probability of finding the device in the P or AP state at a given time as a function of external magnetic-field bias.

Figure 3: V-MTJ/CMOS neuron architectural blocks: (a) V-MTJ excitability circuit for generating the excitation window through voltage-controlled MTJ switching dynamics. (b) Membrane dynamics circuit for membrane charging, threshold integration, and spike generation. (c) Spike-triggered increment circuit for recovery accumulation and firing adaptation. (d) Recovery circuit for implementing recovery-controlled leakage and temporal adaptation dynamics.

Panel of Figure 4 — Figure 4: Simulated firing behaviors of the proposed V-MTJ/CMOS neuron, demonstrating its ability to emulate diverse biologically inspired firing patterns. (a) Tonic bursting, characterized by repetitive burst events. (b) Tonic spiking, exhibiting sustained periodic spike generation. (c) Phasic bursting, producing a single burst event. (d) Phasic spiking, producing a single spike. (e) Spike latency, characterized by a delayed spike.

Panel of Figure 5 — Figure 5: Software emulation of multi-pattern neural dynamics (a) Simulated tonic-bursting response showing repetitive clusters of high-frequency spikes interspersed with silent refractory periods under a constant input stimulus ( $I_{in}=1.0$ ). (b) Simulated phasic-bursting response exhibiting a transient high-frequency burst at stimulus onset followed by sustained quiescence.

Dataset	LIF	Tonic Burst	Phasic Burst	LIF	Tonic Burst	Phasic Burst
	Classification Accuracy (%)			Spikes per Inference (Mean $\pm$ SD)
MNIST	97.80	97.59	97.59	9,326 $\pm$ 3,581	5,177 $\pm$ 568*	3,449 $\pm$ 147 *
Fashion-MNIST	85.21	85.73	86.76	42,861 $\pm$ 12,948	13,707 $\pm$ 3,708*	4,916 $\pm$ 647 *
Breast Cancer	97.39	97.39	97.39	765 $\pm$ 423	444 $\pm$ 81*	328 $\pm$ 16 *
IRIS	96.77	96.77	96.77	2,123 $\pm$ 332	750 $\pm$ 56*	431 $\pm$ 8 *

Table 1: Comparison of classification accuracy and spike activity across neuron models. SNNs utilizing bursting dynamics (Fig. 5 ) drastically reduce the network spike count required per inference compared to the LIF baseline, without suffering notable degradation in task performance. (

*\ p<0.001

versus LIF baseline, Welch’s t-test.)

Neuromorphic Computing

Neuromorphic computing uses brain-inspired, event-driven algorithms and hardware to process information with low power and latency.

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Department of Electrical and Computer Engineering · Oakland University, Rochester, MI USA · Department of Physics

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Spiking neural networks encode information in spike timing and offer a pathway toward energy efficient artificial intelligence. However, a key challenge in spiking neural networks is realizing nonlinear and expressive computation in compact, energy-efficient hardware without relying on additional circuit complexity. In this work, we examine nonlinear computation in a CMOS+X spiking neuron implemented with a magnetic tunnel junction connected in series with an NMOS transistor. Circuit simulations of a multilayer network solving the XOR classification problem show that three intrinsic neuronal properties enable nonlinear behavior: threshold activation, response latency, and absolute refraction. Threshold activation determines which neurons participate in computation, response latency shifts spike timing, and absolute refraction suppresses subsequent spikes. These results show that magnetization dynamics of MTJ devices can support nonlinear computation in compact neuromorphic hardware.

Abstract

Neuromorphic Computing

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