Inspector: Conversational and Lightweight Analyzer of Analog Circuit Layouts Using LLM and CNNs

Abril Cano Castro; Giuseppe Chiari; Michele Piccoli; Federico Viola; Davide Zoni

cs.LGSep 28, 2026

Inspector: Conversational and Lightweight Analyzer of Analog Circuit Layouts Using LLM and CNNs

Authors: Abril Cano Castro, Giuseppe Chiari, Michele Piccoli, Federico Viola, Davide Zoni

Organizations: DEIB Politecnico di Milano Milano, Italy

Abstract

The integration of artificial intelligence into computer-aided design frameworks has sparked a shift in the design of analog integrated circuits (ICs), transitioning the field from using manual and algorithmic-based solutions to adopting automated and intelligent paradigms. In this scenario, the GDSII file represents the industry-standard database containing the ultimate and most accurate source of information of the analog circuit, encapsulating the complex physical geometries and parasitic realities that define tape out performance. This paper proposes a novel framework that combines fine-tuned LLMs and CNNs to analyze GDSII files of analog circuits, enabling a conversational interface between the tool and the designers. Experimental results using thousands of analog designs across four realistic tasks demonstrate that the proposed solution outperforms state-of-the-art general-purpose massive VLMs by a significant margin (up to 81%), thus providing a lightweight solution to the problem of GDSII analysis.

Figures & tables

Category	Circuit Type	Variants	Avg. Devices	NMOS	PMOS	CAP	RES	Total Devices
Single Component	Capacitor	$5\,000$	$1$	–	–	$1$	–	$5\,000$
	NMOS Transistor	$5\,000$	$1$	$1$	–	–	–	$5\,000$
	PMOS Transistor	$5\,000$	$1$	–	$1$	–	–	$5\,000$
	Resistor	$5\,000$	$1$	–	–	–	$1$	$5\,000$
	Subtotal	$20\,000$	–	–	–	–	–	$20\,000$
Base Circuits	Ahuja OTA	$995$	$15$	$10$	$4$	$1$	–	$14\,925$

TABLE I : Dataset composition. For each category, the table reports the circuit types, the number of layout variants, the average number of devices per variant, and the average per-device-type counts (NMOS, PMOS, capacitors, and resistors).

Complexity	Task ID	Task Description
Easy	A	Identification of single component devices
Easy	A	(capacitors, resistors, NMOS, PMOS)
Medium	B	Identification of base circuit topologies
	B	(OTAs, filters, regulators, gate drivers)
	C	Component counting and enumeration
	C	in base circuits

TABLE II : Task descriptions, organized by complexity (i) Easy, (ii) Medium, and (iii) Hard.

Task	Inspector				InternLM-4KHD [ 30 ]			GPT-5.2 [ 31 ]
	parameters	$t_{t+f}$	$t_{i}$	accuracy	parameters	$t_{i}$	accuracy	parameters	$t_{i}$	accuracy
	(# in billions)	(mm:ss)	(ss)	(%)	(# in billions)	(ss)	(%)	(# in billions)	(ss)	(%)
A	$\sim 1$	$29$ : $25$	$1.19$	$97$	$7$	$0.52$	$41$	$50\,000^{\ast}$	$2.3$	$100$
B	$\sim 1$	$28$ : $48$	$0.24$	$91$	$7$	$0.54$	$16$	$50\,000^{\ast}$	$2.8$	$83$
C	$\sim 1$	$19$ : $04$	$3.65$	$99$	$7$	$0.54$	$18$	$50\,000^{\ast}$	$4$	$20$
D	$\sim 1$	$15$ : $37$	$2.62$	$92$	$7$	$0.52$	$24$	$50\,000^{\ast}$	$3.8$	$26$

TABLE III: Comparison of Inspector with state-of-the-art VLMs in terms of parameters, runtime, and accuracy.

Fig. 3 : Layout of an HPF. The labels are generated to contain the whole bounding box of the device.

Task	mAP@0.5	mAP@0.5:0.95	Precision	Recall
	(%)	(%)	(%)	(%)
A	$99.4$	$99.48$	$99.91$	$100$
B	$99.3$	$99.34$	$98.43$	$98.12$
C	$99.5$	$98.66$	$99.99$	$99.99$
D	$99.4$	$93.13$	$99.55$	$99.40$

TABLE IV : Inspector ’s CNN detection performance.

Task	Accuracy (%)		Params	Fine-t. Time	Inf. Time
	T-ID	R-R	(#B)	(s)	(mm:ss)
A	$97.95$	$100$	$1$	$17$ . $32$	$01:18$
B	$93.68$	$98.41$	$1$	$14$ . $46$	$00:19$
C	$100$	$99.58$	$1$	$15$ . $04$	$04:03$
D	$100$	$92.98$	$1$	$14$ . $40$	$02:59$

TABLE V: Inspector ’s LLM performance metrics.

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Sep 28, 2026, cs.LGJ/K move · Enter open · S save

THEIA: A Multimodal Dataset and Benchmark for Vision-Language Analysis of Layout

Giuseppe Chiari, Michele Piccoli, Federico Viola, Davide Zoni

DEIB Politecnico di Milano Milan, Italy, 20133

Analog Design Layouts Recent Vision-Language Models Vision-Language Foundation Models Multimodal Dataset

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The integration of artificial intelligence into computer-aided design frameworks has sparked a shift in the design of analog integrated circuits (ICs), transitioning the field from using manual and algorithmic-based solutions to adopting automated and intelligent paradigms. In this scenario, the GDSII file represents the industry-standard database containing the ultimate and most accurate source of information of the analog circuit, encapsulating the complex physical geometries and parasitic realities that define tape out performance. This paper proposes THEIA, a novel dataset containing thousands of layout images paired with question-answer conversations, along with a benchmark that employs a fine-tuned vision-language model (VLM) to analyze GDSII files of analog circuits, enabling designers to interact with and query physical layouts as intuitive, meaningful entities. Experimental results using thousands of analog designs across five realistic tasks demonstrate that the proposed fine-tuned VLM outperforms state-of-the-art general-purpose VLMs by a significant margin (up to 73%), highlighting a fundamental gap between general-purpose multimodal reasoning and domain-specific layout understanding.

Abstract

Explore similar work

THEIA: A Multimodal Dataset and Benchmark for Vision-Language Analysis of Layout

PANDA: An LLM-Enhanced Performance-Driven Analog Design Framework Bridging Design Intent and Layout Generation

AaLLM: An End-to-End Analog Circuit Design Framework from Topology Generation to Sizing Using Large Language Models