RepTC: Representation-Aware Optimization for Efficient Traffic Classification on Edge IoT Devices
Organizations: Department of Naval, Electrical, Electronic and Telecommunications Engineering (DITEN), University of Genoa, 16126 Genoa, Italy
Abstract
Traffic classification (TC) is crucial to secure Internet of Things (IoT) networks, whose edge nodes often operate under privacy, bandwidth, and energy constraints. Yet, encrypted payloads and limited computing power make accurate, real-time TC a challenging task. Existing learning-based TC approaches often fix the input configuration a priori, even though it directly influences both predictive performance and computational cost. This paper presents RepTC, a representation-aware hardware-constrained strategy that addresses session-level TC through joint model and input optimization. The method co-optimizes network architecture, session length, and header preprocessing; this enables joint control of model complexity, input scale, and data representation within a unified resource-constrained design space. The proposed approach enforces microcontroller-class constraints on memory, model size, and computation, and yields compact models deployable on low-power edge devices. A gateway monitors traffic by aggregating sessions and either performs inference locally or offloads to a low-power edge node. Both scenarios are validated on heterogeneous embedded hardware, including a Raspberry Pi 3B+, STM32 Nucleo-F401RE, and XIAO ESP32-C3, spanning Cortex-A, Cortex-M, and RISC-V processor architectures; measured inference latency ranges from 0.63 to 18.59 ms, with MCU-side inference energy between 0.50 and 1.41 mJ per session. RepTC yields configurations that achieve high accuracy on a variety of established benchmarks: 96.21% on ISCX VPN-nonVPN, 99.62% on USTC-TFC2016, and 99.97% on Edge-IIoTset; at the same time, model size and computational requirements were reduced by up to three orders of magnitude compared with state-of-the-art methods. The results show that representation-aware optimization can improve efficiency while preserving competitive classification performance.
Figures & tables
| Architecture Design | Input Representation | |||||||
| Work | Gran. | Model | Design Strategy | Header Preprocessing | Header Fields Used | Input Shape | Input Size Selection | Hardware Aware |
| [ 8 ] | Packet | CNN/MLP | Search | IP anonym. | Fixed | 600B | Fixed | ✗ |
| [ 13 ] | Packet | 1D-CNN | Manual | Eth. removal + IP anonym. + UDP zero-pad | Fixed | 1500B | Fixed | ✗ |
| [ 1 ] | Flow | Cascaded BLN | Manual | MAC/IP/port zero | Fixed | 784B | Fixed | ✗ |
| [ 7 ] | Flow | 1D-CNN | Search | None reported | Fixed | 784B | Fixed | ✗ |
| [ 20 ] | Flow | CapsNet | Manual | IP zero | Fixed | 784B | Fixed | ✗ |
| Operation | S1 | S2 | S3 | S4 | S5 | S6 | S7 | S8 |
| Eth. Rem. | ✓ | ✓ | ✓ | ✓ | ||||
| MAC Zero | ✓ | ✓ | ✓ | ✓ | ||||
| IP Anon. | ✓ | ✓ | ✓ | ✓ | ||||
| IP Zero | ✓ | ✓ | ✓ | ✓ | ||||
| Port Zero | ✓ | ✓ | ✓ | ✓ |
| # | Layer | Input Dim | Filt/Units | Ker/Pool | Str | Pad |
| RepTC-ISCX model (ISCX VPN-NonVPN dataset) | ||||||
| Params: 54.67k , M-Tens: 2.55k , FLOPs: 305.87k , , | ||||||
| 1 | Conv1D + ReLU | 218 x 1 | 69 | 7 | 6 | same |
| 2 | Conv1D + ReLU | 37 x 69 | 61 | 4 | 7 | valid |
| 3 | Conv1D + ReLU | 5 x 61 | 48 | 1 | 1 | same |
| 4 | Conv1D + ReLU | 5 x 48 | 132 | 5 | 5 | same |
| Method | Input | Acc. (%) | F1 W (%) | F1 m (%) | Params. (M) | M-Tens. (K) | FLOPs (M) |
| ISCX VPNNon-VPN Dataset | |||||||
| RepTC-ISCX | sess. | 96.21 0.51 | 96.24 0.51 | 95.33 0.48 | 0.05 | 2.55 | 0.30 |
| [ 6 ] | Sess. | 96.60 | 96.63 | - | 0.09 | 20.12 | 10.08 |
| [ 44 ] | Sess. | 96.59 | 96.54 | - | 0.09 | 20.12 | 10.08 |
| [ 46 ] | Sess. | - | 91.80 | - | 0.22 | 313.60 | 267.22 |
| [ 52 ] | Sess. | 99.79 | 99.80 | - | 2.06 | 200.70 | 3152.27 |
| Setting | Search Over | Results | Wall- clock (h) | |||||||
| Acc. (%) | F1 m (%) | F1 w (%) | Par. (M) | M-Tens. (K) | FLOPs (M) | |||||
| Restricted search ablations | ||||||||||
| Architecture search | ✓ | 784 B | 92.74 0.76 | 92.33 0.58 | 92.79 0.74 | 0.03 | 3.02 | 0.50 | 17.76 | |
| Architecture+ search | ✓ | ✓ | 784 B | 93.12 0.77 | 92.45 0.67 | 93.15 0.75 | 0.03 | 2.46 | 0.26 | 16.76 |
| Architecture+ search | ✓ | ✓ | 93.39 0.80 | 92.69 0.74 | 93.44 0.78 | 0.04 | 1.12 | 0.46 | 17.26 | |
| Decoupled search | ||||||||||
| Level | Limit | Acc. (%) | F1 m (%) | F1 w (%) | Par. (M) | M-Tens. (K) | FLOPs (M) | ||
| Maximum tensor size / RAM | |||||||||
| Constrained | 2K | 328 B | 93.65 0.21 | 92.55 0.45 | 93.44 0.25 | 0.04 | 1.27 | 0.26 | |
| Relaxed | 8K | 742 B | 96.12 0.32 | 95.54 0.65 | 96.10 0.27 | 0.04 | 4.27 | 0.46 | |
| Computational cost / FLOPs | |||||||||
| Constrained | 0.25M | 234 B | 92.65 0.42 | 92.55 0.61 | 92.44 0.33 | 0.05 | 0.91 | 0.24 | |
| Relaxed | 1.00M | 236 B | 96.65 0.20 | 96.05 0.55 | 96.54 0.17 | 0.06 | 2.80 | 0.76 | |
| Specification | Raspberry Pi 3B+ | STM32 Nucleo- F401RE | XIAO ESP32-C3 |
| CPU/Core | Cortex-A53 | Cortex-M4 | RISC-V |
| Clock | 4 1.4 GHz | 84 MHz | 160 MHz |
| RAM | 1 GB LPDDR2 | 96 KB SRAM | 400 KB SRAM |
| Flash / Storage | microSD (ext.) | 512 KB Flash | 4 MB Flash |
| OS / SDK | Raspbian Lite | STM32Cube.AI | ESP-IDF / TFLM |
| Connectivity | Ethernet, UART | UART | USB/UART |
Edge Inference
Edge inference runs trained AI models on nearby devices such as phones, cameras, robots, and embedded computers under tight resource and latency limits.
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