cs.ETOct 5, 2026
SaveSynapse Loss Estimation for the BrainScaleS Wafer-scale Neuromorphic System
Organizations: Chair of Highly-Parallel VLSI-Systems and Neuro-Microelectronics, TUD Dresden University of Technology, Dresden, Germany
Abstract
Neuromorphic hardware combines memory (synapses) and computation (neurons) into the same silicon substrate to avoid the von-Neumann bottleneck. This way, neuromorphic computing aims to make computational neuroscience simulations and AI processing faster and more energy-efficient. The common crossbar architecture integrates a synapse matrix (analog, mixed-signal or digital) with a neuron array into a neurosynaptic core, whereas multiple cores are interconnected via a dedicated spike routing network. One of such neuromorphic architecture is the BrainScaleS wafer-scale system which allows the realization of very flexible network architecture, supporting both dense and sparse connectivity by highly configurable neurosynaptic cores. Yet, when network models from computational neuroscience are mapped to the BrainScaleS wafer, synapse loss can occur which means that for some model synapses no hardware synapse is available due to the restricted connectivity of the hardware. In this work we analyze the synapse loss when mapping uniform random networks to BrainScaleS both theoretically and empirically. We first develop a methodology to estimate maximum-sized networks without synapse loss based on probability distributions and the hardware's synapse routing architecture. Next, we adopt the methodology to predict the synapse loss for denser or larger network models. Then, we compare the predictions with results from actual runs of the mapping software: The results show the capabilities and limitations of the BrainScaleS system itself and spot shortcomings of the current mapping algorithms. The developed methodology can be helpful in multiple ways: to find the optimal settings when mapping a given network model to BrainScaleS, to act as a benchmark for the mapping software, and as tool for design space exploration for new hardware.
Figures & tables
Figure 1: BrainScaleS wafer-scale hardware: A Assembled wafer module. B Wafer after post-processing with reticles containing 8 HICANNs each. C HICANN ASIC with neuron and synapse blocks highlighted. The on-wafer routing network is located left and right of the synapse arrays and between them. Figure from [ 11 , Fig. 1] with permission.
Figure 2: On-wafer routing network: A reticle (top left) contains HICANNs with a grid of horizontal and vertical buses for spike event routing, which can be connected through sparse crossbar switches. Spikes are detected in neuron circuits, processed by a priority encoder and a merger tree, and then injected with a 6-bit address into a horizontal bus via a sending repeater. The analog serial spike events are re-generated at HICANN edges in repeater circuits. At target HICANNs, the events are routed via further static sparse switches to synapse drivers and thus the synapse arrays. The dark blue line shows an example route from neuron A to neuron B.
Figure 3: Spike processing in synapse array: Spikes arrive as 6-bit pulses in the synapse driver. The 2 MSB are compared to the 2-bit configuration per strobe pattern A, B, C, D (also called half synapse rows ). Upon a match, strobe pulses are sent to the synapse array. The pulse height is controlled by parameter (configurable per synapse row), while the pulse length is determined by a STP circuit in the synapse driver. In the synapse circuits, the 4 LSB of the 6-bit event are compared to a 4-bit value in SRAM. In case of a match, a current pulse is generated with its height depending on a 4-bit weight and . This current pulse is transmitted to either the left or right synaptic input circuit of the neuron in the same column (configured per synapse row).
Figure 4: Mapping steps
| Neuron size | 4 | 8 | 12 | 16 | 32 | 64 |
|---|---|---|---|---|---|---|
| Neuron width | 2 | 4 | 6 | 8 | 16 | 32 |
| Synapses per half row | 1 | 2 | 3 | 4 | 8 | 16 |
Table 1: Number of synapses per half synapse row
Figure 5: Example: Required resources for uniform random networks. This figure illustrates how to compute the number of required hardware resources to realize all synapses from an on-wafer routing source to all target neurons on a HICANN. Parameters used here: connection probability , target neurons per HICANN of size 8. A The number of input synapses per target follows a binomial distribution ( sources per 2 MSB address pattern). B Probability that is the maximum number of synapses per target for all target neurons. C Probability that half synapse rows are required to realize all synapses from the sources per 2 MSB address pattern. D Number of half synapse rows required for all four 2 MSB patterns. E Number of required synapse drivers.
| symbol | description | value / value range |
| connection probability | ||
| probability distribution of random variable | ||
| cumulative distribution function | ||
| survival function | ||
| synapses | - | |
| half synapse rows | - |
Table 2: List of symbols and constants
Figure 6: Realizable uniform random networks on HICANN. Left: Expected number of source neurons for which all synapses to target neurons on a HICANN can be realized depending on the connection probability and different mapping scenarios (Number of target neurons and neuron size). The upper limit of source neurons is given as 14,336$$ . Right: Expected number of realized synapses per HICANN for the data from the left according to eq. 27 . The right axis shows the relative utilization of the overall synapses per HICANN.
Figure 7: Comparison to hardware architecture with 6-bit synapse address decoder. The HICANN decodes the upper 2 bits of the 6-bit neuron addresses for each half synapse row and only 4 bits in the synapse. This approach is compared to a setup where all 6 bits are decoded in the synapse. Left: Expected number of source neurons for which all synapses to target neurons on a HICANN can be realized for 64 target neurons of size 8. Right: Expected number of realized synapses per HICANN and synapse utilization.
Figure 8: Realizable uniform random networks on HICANN with constraints. In real experiments, only 59 out of 64 addresses can be used for real source neurons, as described in section 2.5 . We compare the realizable uniform networks with 59 sources (darker lines) to the previously assumed 64 sources (lighter lines) per on-wafer routing source. Left: Expected number of source neurons for which all synapses to target neurons on a HICANN can be realized depending on the connection probability and different mapping scenarios (Number of target neurons and neuron size). MaxC denotes the maximum number of source neurons in the constrained case: . Right: Expected number of realized synapses and synapse utilization per HICANN for neuron size 8. The dotted lines show the cases affected by the synapse driver chain length limitation: here, all cases are marked where the probability is higher than that more than 5 drivers per routing source are required.
Figure 9: Maximum recurrent uniform random networks. The figure shows the expected maximum network size of uniform random networks that can be implemented on one wafer for different connection probabilities and mapping scenarios. We assume that all inter-HICANN connections can be realized during the on-wafer routing step ( Section 2.1.2 ). For this study, the number of source neurons per routing source is consistent with the number neurons sending on one routing bus and depends on the mapping scenario. In contrast, previous studies (e.g., fig. 6 and fig. 8 ) always use the same number (64 or 59) of source neurons per routing source.
| neuron size | 4 | 8 | 12 | 16 |
|---|---|---|---|---|
| neurons per HICANN | 118 | 59 | 40 | 30 |
| nouting sources per HICANN | 2 | 1 | 1 | 1 |
| 2-MSB patterns per routing source | 4 | 4 | 3 | 2 |
| maximum number of HICANNs | 112 | 224 | 224 | 224 |
| maximum number of neurons |
Table 3: Mapping setups to estimate maximum realizable recurrent networks in fig. 9 . For neuron size 12 there are maximum 40 neurons per HICANN and not 42 as compound neurons may not exceed the bounds of neuron blocks containing 64 neurons per priority encoder.
Figure 10: Synapse loss approximation for feedforward uniform random networks. For different connection probabilities and mapping scenarios (number and size of target neurons on one HICANN), the synapse loss is estimated depending on the number of source neurons per HICANN. As in fig. 8 , we consider the realistic case that only 59 of 64 addresses per routing source can be used for neurons ( Section 2.5 ). The crosses mark the expected number of source neurons that can be implemented without synapse loss, as determined in fig. 8 . The gray dashed lines (highlighted by the gray area underneath) denote the synapse loss due to the limited number of 224 synapse drivers per HICANN: Once there are more than 224 routing sources, all synapses are lost for the fraction of routing sources exceeding this limit.
Figure 11: Synapse loss approximation for recurrent networks with uniform random connectivity. Estimated synapse loss of recurrent networks depending on the network size for different connection probabilities and mapping scenarios. We assume that all inter-HICANN connections can be realized during the on-wafer routing step ( Section 2.1.2 ). As in fig. 9 , the number of source neurons per routing source is consistent with the number neurons sending on one routing bus and depends on the mapping scenario. The crosses mark the expected network size that can be realized without synapse loss. Note that the lines end at the maximum network size per mapping scenario, which depends on the number of neurons per HICANN. The curves for neuron size 4 are cropped at the x-axis limit, please see fig. 13 for the full plot.
Figure 12: Synapse loss of recurrent uniform random networks: mapping versus theory. Relative synapse loss for recurrent networks with connection probability (left) and (right) at different network sizes. Labels: final – synapse loss at the end of the mapping, on-wafer – synapse loss after the on-wafer routing step, estimated – synapse loss approximation according to sections 2.4 and 11 . The vertical dashed line denotes the transition from using neuron size 8 to 4, as in [ 8 , Fig. 8.8] . For networks with more than 36K neurons could not be mapped due to memory limitations. Note that the estimated curves look much smoother as they use a step size of 59 neurons, while the actual mapping is performed with larger steps.
Appendix figures & tables2 assets
Supplementary material from the paper’s appendix.
Appendix
Figure 13: Synapse loss approximation for recurrent networks with uniform random connectivity with 118 neurons per HICANN. Estimated synapse loss of recurrent networks depending on the network size for different connection probabilities for the mapping scenario with 118 neurons per HICANN of size 4. In comparison to fig. 11 , this plot shows the curves for different in one plot and up to the maximum network size for this mapping scenario.
Figure 14: Synapse loss approximation - Comparison of address decoding architectures. We compare the estimated synapse loss for the address decoding of the HICANN (2 bits per half synapse row, 4 bits per synapse) with a 6-bit decoder in the synapse like: For different connection probabilities and a fixed mapping scenario (64 neurons of size 8), the synapse loss is estimated depending on the number of source neurons per HICANN. Here, we assume 64 addresses per routing source and neglect hardware limitations ( Section 2.5 ). The crosses mark the expected number of source neurons that can be implemented without synapse loss, as determined in fig. 7 . The gray dashed lines (highlighted by the gray area underneath) denote the synapse loss due to the limited number of 224 synapse drivers per HICANN: Once there are more than 224 routing sources, all synapses are lost for the fraction of routing sources exceeding this limit.