CircuitGate: Logic-Consistent Circuit-Level Functional Modeling for And-Inverter Graphs

Qifan Zhang; Ruijie Li; Fangzhou Zhang; Qian Ma; Hui Li; Furui Zhan; Yongpeng Wang; Liying Hao

cs.LGOct 7, 2026

CircuitGate: Logic-Consistent Circuit-Level Functional Modeling for And-Inverter Graphs

Authors: Qifan Zhang, Ruijie Li, Fangzhou Zhang, Qian Ma, Hui Li, Furui Zhan, Yongpeng Wang, Liying Hao, +1 more

Organizations: Dalian Maritime University · The Hong Kong University of Science and Technology (Guangzhou)

Abstract

And-Inverter Graphs (AIGs) are fundamental representations for logic synthesis and verification in Electronic Design Automation (EDA). As structured representations of complex digital systems, AIGs require models to capture functional dependencies beyond local structure and remain robust to functionality-preserving transformations. In learning-based AIG representation, existing approaches are predominantly based on GNNs and rely on local gate-level message passing, limiting their ability to capture circuit-level functional context and making the learned representations sensitive to topology-specific patterns. Therefore, we propose CircuitGate, a function-aware AIG representation learning framework that advances from gate-level semantics to circuit-level functional modeling. CircuitGate explicitly encodes global primary-input (PI) support and models support-overlap-aware reconvergence between fanins, while incorporating logic-inspired Boolean constraints to encourage functionally consistent representations. We evaluate CircuitGate on the large-scale ForgeEDA benchmark and further validate it on the EPFL and ITC'99 benchmarks. Across equivalent-gate identification and signal-probability prediction tasks, CircuitGate consistently outperforms existing methods, achieving up to 21.7% and 14.2% reductions in MAE, respectively. Under direct ForgeEDA-to-OpenABC transfer without fine-tuning, CircuitGate also achieves the best equivalent-gate identification performance, demonstrating strong cross-dataset generalization. These results demonstrate the effectiveness of modeling circuit-level functional dependencies beyond local topology.

Figures & tables

Figure 1: Motivating comparison between prior gate-level AIG representation methods and CircuitGate. Existing approaches mainly rely on local structural message passing, resulting in incomplete functional context and limited logic consistency, while CircuitGate explicitly models circuit-level functional dependencies and improves representation consistency.

Figure 2: Overview of the CircuitGate framework.

Model	Venue	ForgeEDA				EPFL				ITC’99
Model	Venue	MAE $\downarrow$	MSE $\downarrow$	AP $\uparrow$	F1 $\uparrow$	MAE $\downarrow$	MSE $\downarrow$	AP $\uparrow$	F1 $\uparrow$	MAE $\downarrow$	MSE $\downarrow$	AP $\uparrow$	F1 $\uparrow$
GCN	ICLR’17	0.1522	0.0537	0.0141	0.0368	0.2364	0.1060	0.2952	0.1478	0.2129	0.1145	0.6396	0.6434
GAT	ICLR’18	0.1886	0.0762	0.0102	0.0312	0.3086	0.1517	0.1694	0.2930	0.2186	0.1205	0.5370	0.6873
GraphSAGE	NeurIPS’17	0.1311	0.0424	0.0175	0.0228	0.1117	0.0368	0.4118	0.4062	0.2188	0.1203	0.5501	0.6883
DeepGate	DAC’22	0.1440	0.0526	0.0108	0.0296	0.1183	0.0368	0.4042	0.2705	0.1318	0.0516	0.7168	0.8133
DeepGate2	ICCAD’23	0.2914	0.1237	0.0154	0.0360	0.2804	0.1227	0.1316	0.0109	0.2173	0.0977	0.6717	0.7511

Table 1: Equivalent-gate identification results. Best and second-best results are bold and underlined.

Model	ForgeEDA	EPFL	ITC’99
GCN	0.0422	0.1637	0.1688
GAT	0.0396	0.1386	0.0879
GraphSAGE	0.0446	0.0536	0.0231
DeepGate	0.1604	0.0910	0.0831
DeepGate2	0.1408	0.0923	0.0717
DeepGate3	0.0315	0.0625	0.0161

Table 2: Signal-probability prediction results (MAE).

Variant	ForgeEDA				EPFL				ITC’99
Variant	MAE $\downarrow$	MSE $\downarrow$	AP $\uparrow$	F1 $\uparrow$	MAE $\downarrow$	MSE $\downarrow$	AP $\uparrow$	F1 $\uparrow$	MAE $\downarrow$	MSE $\downarrow$	AP $\uparrow$	F1 $\uparrow$
w/o Circuit-Level Context	0.0477	0.0135	0.0429	0.1118	0.0914	0.0234	0.4409	0.4403	0.0850	0.0243	0.9755	0.9270
w/o PI-Dependency Encoding	0.0582	0.0184	0.0220	0.0634	0.0864	0.0248	0.5211	0.3708	0.0691	0.0210	0.9454	0.9317
w/o Reconvergence	0.0561	0.0175	0.0229	0.0670	0.0872	0.0243	0.5472	0.3964	0.0833	0.0256	0.9661	0.9084
w/o Logic Constraints	0.0495	0.0135	0.0351	0.1007	0.0817	0.0220	0.5203	0.5513	0.0864	0.0201	0.9659	0.8985
Full	0.0433	0.0118	0.0469	0.1149	0.0683	0.0163	0.6503	0.6543	0.0622	0.0140	0.9823	0.9467

Table 3: Ablation study on the equivalent-gate identification task on ForgeEDA, EPFL, and ITC’99.

Model	Params. (M) $\downarrow$	EQ MAE $\downarrow$	Neural inf. (ms) $\downarrow$	AEC $\downarrow$
GraphSAGE	0.0173	0.1311	9.1204	1.1957
AIGer	0.5603	0.1472	10.5431	2.5137
FuncGNN	0.9765	0.1075	11.2865	2.0854
MGVGA	1.1050	0.0563	12.2759	1.2031
DeepGate3	4.7272	0.0553	73.2356	8.0999
DeepGate4	4.6465	0.1361	172.2620	46.8177

Table 4: Accuracy–efficiency comparison on ForgeEDA

Model	resyn2	dc2	rewrite	refactor
GCN	0.6506	0.5967	0.7129	0.7322
GAT	0.6241	0.5836	0.8174	0.8449
GraphSAGE	0.6631	0.6272	0.7616	0.7948
DeepGate	0.4278	0.4114	0.5219	0.5374
DeepGate2	0.4637	0.4105	0.5232	0.5392
DeepGate3	0.6784	0.6572	0.7672	0.7842

Table 5: Representation consistency under synthesis-induced topology transformations, measured by CKA (

\uparrow

Figure 3: Parameter sensitivity of CircuitGate on equivalent-gate identification. Each panel varies one hyperparameter, with the selected setting highlighted in bold orange.

Appendix figures & tables10 assets

Supplementary material from the paper’s appendix.

Appendix

Modality	#Samples	Node Range	Edge Range	Format	Contents
Code Repository	1,189	–	–	.v	Verilog code with comments and specifications
PM Netlist	4,450	–	–	.v	Post-mapping netlists
				.rpt	Area, path-delay, and power reports
Placed Netlist	4,450	–	–	.v / .def	Placed netlists
				.rpt	Area, WNS, TNS, and power reports
AIG	4,450	[5–386,996]	[1–753,750]	.aig	Raw AIG files

Appendix

Table 6: Statistics of the ForgeEDA dataset Shi et al. (2025a) .

Data Type	#Samples	Node Range	Edge Range	#Gate Pairs	Contents
Original AIGs	19	[320–101,954]	[496–159,073]	–	Original EPFL circuits
Processed Parents	16	–	–	–	Parent circuits producing subcircuits
Processed Subcircuits	101	[519–5,000]	[716–9,305]	1,514,460	Model input graphs
Train Split	51	[519–5,000]	–	765,000	9 parent circuits
Validation Split	27	[2,426–5,000]	–	405,000	3 parent circuits
Test Split	23	[1,082–5,000]	–	344,460	4 parent circuits

Appendix

Table 7: Statistics of the processed EPFL benchmark dataset.

Data Type	#Samples	Node Range	Edge Range	#Gate Pairs	Contents
Original AIGs	20	[47–140,638]	[65–217,943]	–	Original ITC’99 circuits
Processed Parents	16	–	–	–	Parent circuits producing subcircuits
Processed Subcircuits	57	[79–5,000]	[113–7,321]	74,906	Model input graphs
Train Split	38	[79–5,000]	[113–7,200]	41,564	10 parent circuits
Validation Split	7	[538–5,000]	[720–6,814]	14,934	3 parent circuits
Test Split	12	[1,154–5,000]	[1,229–7,321]	18,408	3 parent circuits

Appendix

Table 8: Statistics of the processed ITC’99 benchmark dataset.

Dataset	Evaluated Pairs	Positive Pairs	Positive Rate
ForgeEDA	153,270,272	712,168	0.464648%
EPFL	344,460	36,017	10.4561%
ITC’99	18,408	9,204	50.0000%

Appendix

Table 9: Exact-equivalence pair statistics on the test sets.

Variant	MAE $\downarrow$	MSE $\downarrow$	AP $\uparrow$	F1 $\uparrow$
Full	0.04330	0.01180	0.04690	0.11490
Per-circuit PI permutation	0.04281	0.01204	0.04540	0.11447
Unsigned support	0.04416	0.01287	0.04205	0.05849
Cardinality/Coverage only	0.05360	0.01724	0.02781	0.07850

Appendix

Table 10: Additional controls for PI-support encoding on ForgeEDA.

Figure 4: Cross-dataset generalization from ForgeEDA to OpenABC. All methods are directly evaluated on OpenABC using checkpoints trained on ForgeEDA, without fine-tuning. Lower MAE is better.

Circuit	Nodes	Edges	PIs	$M$	Preproc. (s)	Input-to-cache (s)	Peak RSS (MiB)
simple_spi	1,928	2,694	164	15,984	0.0350	0.0535	362.49
max	6,279	8,632	512	2,373,500	0.3432	0.3691	368.83
mem_ctrl	31,001	47,906	1,187	2,465,821	0.9151	0.9828	419.16
tinyRocket	104,336	152,090	4,561	8,373,687	3.3765	3.5616	566.09
jpeg	233,573	343,382	4,962	4,816,133	4.6663	5.0562	857.41
hyp	420,769	634,848	256	88,956,323	15.0327	15.7461	885.24

Appendix

Table 11: Complete-graph preprocessing scalability.

M

denotes the total number of parity-specific support memberships. Values are medians of three independent fresh-process runs.

Model	resyn2	dc2	rewrite	refactor
GCN	0.3724	0.3721	0.3732	0.3726
GAT	0.3662	0.3696	0.3649	0.3644
GraphSAGE	0.2477	0.2417	0.2447	0.2444
DeepGate	0.2138	0.2275	0.2474	0.2395
DeepGate2	0.2814	0.2805	0.2850	0.2911
DeepGate3	0.1971	0.1933	0.1919	0.1921

Appendix

Table 12: Equivalent-gate identification MAE (

\downarrow

) under synthesis-induced topology transformations. Best and second-best results are bold and underlined, respectively.

Parameter	Value	MAE $\downarrow$	MSE $\downarrow$	AP $\uparrow$	F1 $\uparrow$
$\alpha$	0	0.0457	0.0132	0.0412	0.1235
	0.05	0.0433	0.0118	0.0469	0.1149
	0.1	0.0467	0.0132	0.0453	0.1079
	0.2	0.0437	0.0122	0.0429	0.1126
$\lambda_{\mathrm{logic}}$	0	0.0495	0.0135	0.0351	0.1007
	0.02	0.0448	0.0125	0.0439	0.1239

Appendix

Table 13: Hyperparameter sensitivity on equivalent-gate identification. Bold parameter values denote the default settings, while bold metric values indicate the best result within each parameter group.

Module	Input	Hidden	Output	Dropout
Support $\mathrm{MLP}_{q}$	$2d_{s}+4=132$	128	128	0.1
$\mathrm{MLP}_{s}$	$4d_{h}=512$	128	128	0.1
$\mathrm{MLP}_{g}$	$6+d_{h}=134$	128	128	0.1
Probability head	256	256	1	0.2

Appendix

Table 14: Architecture details of CircuitGate.

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ReDIL-GNN: Resynthesis Domain Incremental Learning for Circuit Graph Neural Networks

Rupesh Raj Karn, Johann Knechtel, Ozgur Sinanoglu

Center for Cyber Security, New York University, Abu Dhabi, UAE.

Differentiable Logic Gate Networks Gnn-Based Detectors Circuits Graph Neural Networks Class-Incremental Learning Neural Network+1

Open paper AskPDF arXiv

Logic resynthesis preserves circuit functionality while changing gate vocabulary, topology, and structural statistics, creating domain shift for circuit graph neural networks (GNNs) without changing task labels. To study this setting, we introduce ReDIL-GNN, a resynthesis domain-incremental learning framework that adapts a fixed prediction or representation head as new synthesis styles arrive and evaluates retention on all previously observed domains. Because not every shift should be adapted blindly, ReDIL-GNN further introduces the Resynthesis Adaptability Index (RAI), a pre-adaptation score that combines adaptation need, source-equivalence recoverability, structural coverage, and update compatibility. We evaluate supervised hardware-security tasks and representation-learning models using task-native metrics for classifiers and source-equivalence retrieval metrics for embedding models, comparing naive fine-tuning with LwF, Online EWC, MAS, ER, A-GEM, DER++, ER+LwF, and equivalence-guided replay. Across the studied pipelines, RAI separates unsupported shifts from promising updates, ranging from 0.001 for a structurally uncovered GNN-RE ABC-rewrite shift to 0.824 for the best original-only GNN-RE adaptation case. In practice, ReDIL-GNN turns resynthesis-aware circuit learning into a deployment control loop: RAI screens each new synthesis flow before update, guiding whether to reuse the current model, apply retention-aware adaptation, or defer adaptation until the shift is better supported.

Abstract

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