The Missing Fourth Term for the Emulation Tensor Memory Equilibrium (TME) Model: The Residue Deconstruction Cost

Harun Bayraktar; John Gunnels; Peter Caday

cs.AROct 7, 2026

The Missing Fourth Term for the Emulation Tensor Memory Equilibrium (TME) Model: The Residue Deconstruction Cost

Authors: Harun Bayraktar, John Gunnels, Peter Caday

Organizations: NVIDIA Corporation

Abstract

The Tensor-Memory Equilibrium (TME) model of "FP8 is All You Need (Part 1)" calculates the execution time of Ozaki Scheme II emulation of fp64 as the maximum of a tensor-core term and a High-Bandwidth Memory (HBM) traffic term, plus a per-output reconstruction term. However, it omits the per-input deconstruction cost: every streamed fp64 operand must be scaled, rounded, and reduced modulo each of the $r$ moduli on SIMT pipes before any matrix multiply can issue. In this note we add this fourth term, calibrate its constant from the cuBLAS emulation path, and derive a closed-form operational-intensity threshold $\mathrm{OI}^{*} = c_q r P_{\mathrm{fp64}}/(8P_{\mathrm{int}})$ below which emulation cannot match native fp64 regardless of tensor-core throughput. On the NVIDIA B300 GPU the threshold is $\mathrm{OI}^{*}\approx 0.56$ FLOP/B. As a result, GEMV, SpMV, and low-batch GEMV, which are the memory-bound kernels the original paper claims to accelerate, are limited to 0.3-0.9x of native performance, and the 7-point stencil to 1.8x rather than the claimed 3.1x. Dense GEMM is unaffected as expected. We also show that precomputing and storing the residues moves the same cost into the bandwidth term, and we state the instruction count that an implementation would have to achieve to invalidate the bound.

Figures & tables

kernel	$\mathrm{OI}$	$\varphi$	paper’s claim	cap (Eq. 2 )	verdict
SpMV (CSR/ELL)	0.17	1	$1.2\times$	$0.30\times$	regression
7-pt stencil	0.5	$\sim$ 0.5	$3.1\times$	$1.8\times$	claim unreachable
GEMV ( $B{=}1$ )	0.25	1	—	$0.45\times$	regression
batched GEMV, $B{=}2$	0.5	$\sim$ 1	$9.2\times$	$0.89\times$	regression
batched GEMV, $B{=}8$	2	$\sim$ 1	$24\times$	$3.6\times$	$6.7\times$ below claim
dense GEMM	$\geq 50$	$\to 0$	$104\times$	not binding	unaffected (reuse)

Table 1: Speedup caps from Eq. ( 2 ) on the NVIDIA B300 GPU (

r{=}15

c_{q}{=}16

) compared with the speedups claimed in Table 3 of [ 1 ] . The cap assumes

\beta=1

, zero-cost MMAs, and full occupancy, and is therefore an upper bound on what emulation can deliver.

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FP8 is All You Need (Part 1): Debunking Hardware FP64 as the HPC Holy Grail (Sep 3rd version)

Satoshi Matsuoka

Director, RIKEN Center for Computational Science (R-CCS) Kobe, Hyogo, Japan

GPU Kernel Optimization GPU Acceleration High-Performance Computing

Open paper AskPDF arXiv

We argue that on AI-optimised GPUs of the NVIDIA B300 generation and beyond, the FP8 tensor-core matrix operation, composed through CRT-based Ozaki Scheme II, can serve as the dominant matrix-work substrate for the surveyed matrix-dominated FP64 kernel classes at FP64-grade accuracy, with native FP64 recast from a hardware requirement into a derived accuracy guarantee. The claim is conditional: the FP8 op is the candidate dominant multiplication substrate, with a bounded auxiliary set of integer deconstruction/reconstruction work, FP32/Kulisch reductions, data movement and a native-FP64 fallback, organised as a hierarchy from the FP8 op through Ozaki II and the Berkeley dwarfs to applications. The instrument is the Tensor-Memory Equilibrium (TME) model, a Roofline extension with four parameters (compute multiplier

\alpha=3r+1

, bandwidth multiplier

\beta

, reconstruction cost

\gamma

, and the per-input deconstruction cost

c_q

identified in an NVIDIA review) under which, at its upper bound, the reduction to FP8 costs no performance against an ideal native-FP64 machine of equal bandwidth. On-chip tile fusion drives

\beta \to 1

; the deconstruction term sets a threshold intensity below which emulation is conversion-bound. At the fused, engineered-

c_q

bound every surveyed class reaches the memory roof, with two priced exceptions: large dense-square DGEMM sits at a deconstruction floor near 0.50 of the FP8 arithmetic roof (about 235 of 473 TFLOPS on the NVIDIA Rubin GPU), a liftable co-design coordinate, and the 3-D FFT is walled by a per-output integer epilogue at

4.9

6.7\times

its roof in software, recoverable with minor hardware and one moderate ask. Ozaki II lifts the emulated FP64 ceiling from

\approx 1.3

\approx 135

TFLOPS on B300 and

\approx 473

on Rubin; three deconstruction-path hardware options are given; constants are engine-checked.

Abstract

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