LocalTrain: Integer-Only Local Learning for Energy-Efficient CNN Training on Edge FPGAs

Shiqi Ding; Xuanyu Liang; Xinyang Liu; Boyang Li; Zhiqiang Que; Guosheng Hu; Jiayang Li

cs.AROct 12, 2026

LocalTrain: Integer-Only Local Learning for Energy-Efficient CNN Training on Edge FPGAs

Authors: Shiqi Ding, Xuanyu Liang, Xinyang Liu, Boyang Li, Zhiqiang Que, Guosheng Hu, Jiayang Li

Organizations: University of Cambridge · University College London · University of Bristol

Abstract

Local learning reduces cross-layer training dependencies, but an efficient accelerator must still retain operands, accumulate gradients, and select quantization scales. We present an FPGA system that trains a CNN and its regional auxiliary classifiers using a shared integer matrix engine. Compact errors are expanded on chip, gradients are folded tile by tile, and historical scales permit direct output conversion. At 200 MHz, the KV260 prototype achieves 76.57% accuracy on CIFAR-10 and 91.85% on SVHN at approximately 4.20 W mean module power. Effective matrix throughput is 31.22 and 31.57 GMAC/s, respectively. Against the same integer method on Jetson Orin Nano, measured training energy is 40.4% and 42.1% lower, with $1.86\times$ and $1.82\times$ longer runtime; measurements use the respective platform power domains. Selected state checks and matching complete-run prediction counts support functional agreement with the software reference.

Figures & tables

Panel of Figure 1 — Fig. 1: One CNN layer and its local supervision. Dashed paths retain operands; the local head also updates $V$ . No convolutional input gradient is sent to earlier layers.

Panel of Figure 2 — Fig. 2: Hardware organization. Convolution and classifier operations reuse the matrix engine. Regional errors expand in operand supply; numerical and output units share DDR access. Control is dashed; data connections are solid.

Operation	Output indices	Reduction
Conv forward	$(p,c_{\mathrm{out}})$	Kernel, $c_{\mathrm{in}}$
Conv weight gradient ∗	$(c_{\mathrm{out}},c_{\mathrm{in}})$	$n,p$
Local-classifier forward	$(n,k)$	$f$
Local feature error	$(n,f)$	$k$
Classifier weight gradient	$(k,f)$	$n$
Final-classifier forward	$(n,k)$	$f$ in four partitions

TABLE I: Shared-engine mappings.

n

: sample;

p

: spatial position;

c

: channel;

k

: class;

f

: feature.

Resource	Count	Utilization (%)
LUT	92,789	79.23
FF	113,250	48.35
DSP	587	47.04
BRAM (36-Kb equivalents)	122.5	85.07
URAM	20	31.25

TABLE II: KV260 implementation and complete training. Energy is measured on VCC_SOM; energy/sample counts all training presentations across epochs.

Epochs	MMAC/sample	PL s/epoch	GMAC/s	Peak (%)
1–20	69.99	121.53	28.79	28.12
21–30	63.48	90.82	34.95	34.13
31–40	44.60	69.00	32.32	31.56
41–50	35.13	50.65	34.67	33.86

TABLE III: Derived effective matrix throughput on CIFAR-10, using algorithmic MAC counts and measured PL cycles.

Metric	EF-Train [ 7 ]	Venk. [ 10 ]	Ours
Device	ZCU102	Stratix 10 GX	KV260
Clock (MHz)	100	240	200
Precision	FP32	Fixed16	Mixed integer
DSPs	1,315	1,699	587
Accuracy (%)	64.82	73	76.57
Power (W)	6.89 †	20.64 †∗	4.20 ‡

TABLE IV: CIFAR-10 FPGA training over 50 epochs. Networks and power boundaries differ.

CIFAR-10, 50 epochs
Method	Acc. (%)	Time (s)	kJ	MiB
FP32 BP	79.87	2852.11	43.20	544.69
Local FP32	74.43	1198.08	17.62	401.18
Integer local	76.57	2515.06	32.91	297.83
SVHN, 60 epochs
FP32 BP	92.38	5022.51	75.67	544.69

TABLE V: Jetson results in 25 W mode with a configured GPU frequency of 918 MHz. Energy: VDD_IN; memory: peak CUDA allocation.

On-Device Training

On-device training develops methods and systems for adapting or learning models directly on phones, sensors, and edge hardware.

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Spiker-LL: An Energy-Efficient FPGA Accelerator Enabling Adaptive Local Learning in Spiking Neural Networks

Alessio Caviglia, Filippo Marostica, Alessandro Savino, Stefano Di Carlo

Control and Computer Engineering Department, Politecnico di Torino, Turin, Italy

On-Device Training Energy-Efficient ML Spiking Neural Networks Edge ML FPGA-Based Neural Network Acceleration On-Device Inference

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Deploying adaptive intelligence at the edge remains challenging due to the high computational and energy cost of training neural models. Spiking Neural Networks (SNNs) offer a promising alternative, but enabling on-device learning requires hardware-algorithm co-design. This paper presents SPIKER-LL, an FPGA-based SNN accelerator that extends the open-source Spiker+ inference architecture with efficient support for the STSF local learning rule. Through targeted microarchitectural extensions, SPIKER-LL performs inference and online learning with minimal overhead. Across MNIST, F-MNIST, and DIGITS, it achieves up to 93% accuracy, sub-millisecond latency, and less than 0.1 mJ per inference, while remaining DSP-free and highly scalable for edge-FPGA deployments.

Abstract

On-Device Training

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