Saliency-Guided Replay for Continual Learning in Deep Spiking Neural Networks

Francesco Panetta; Federico Di Valerio; Michela Proietti

cs.LGOct 13, 2026

Saliency-Guided Replay for Continual Learning in Deep Spiking Neural Networks

Authors: Francesco Panetta, Federico Di Valerio, Michela Proietti

Organizations: Sapienza University of Rome, Italy · Goethe University Frankfurt, Germany

Abstract

Spiking Neural Networks (SNNs) are promising for energy-efficient neuromorphic computing, but they still suffer from catastrophic forgetting when learning tasks sequentially. This work investigates the integration of Experience Packing and Replay (EPR) as a memory-efficient continual learning strategy for deep SNNs under low-latency constraints. The proposed framework combines Batch Normalization Through Time stabilized VGG9 SNNs with Spike Activation Maps (SAM), which provide forward-only explanations based on spike activity. These explanations are temporally aggregated into spatial attention maps and used to select the most informative image patches for replay, instead of storing full images. Experiments on Split CIFAR10 and Split CIFAR100 show that SAM-guided EPR improves the accuracy-memory trade-off under tight memory budgets, and remains competitive while requiring substantially less storage.

Figures & tables

Figure 1: Comparison of BASE-EPR and EPR-SP using mean and last temporal aggregation across benchmarks. Columns denote benchmark settings, with AvgAcc (top) and AvgForg (bottom). Solid and hatched bars indicate TIL and CIL, respectively; error bars show standard deviation over 3 seeds.

Figure 2: TIL and CIL accuracy versus memory budget for BASELINE and EPR-SP across all benchmarks. At equal budgets, EPR-SP stores more patches than BASELINE stores full samples, yielding higher accuracy at tight and moderate budgets, with the advantage diminishing as memory increases.

Figure 3: TIL and CIL accuracy versus exemplars per class $K$ for BASELINE and EPR-SP on Split-CIFAR10 (5 tasks), CIFAR100/10 (10 tasks), and CIFAR100/20 (20 tasks). At the same $K$ , EPR-SP uses $44\%$ less memory than BASELINE. The gap narrows as $K$ decreases, with EPR-SP outperforming BASELINE at the tightest CIFAR10 budget.

Panel of Figure 4 — Figure 4: Evolution of spatial attribution maps throughout continual learning. For Tasks 1, 5, 10, and 20, we show the input image, the selected patch location, the SAM generated immediately after learning the task from which the patch is selected, and the SAM obtained after training on all 20 tasks.

Storage-Efficient Continual Learning

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Oct 13, 2025J/K move · Enter open · S save

Local Timescale Gates for Timescale-Robust Continual Spiking Neural Networks

Devansh Deep, Ansh Tiwari, Ayush Chauhan

Spiking Neural Networks Online Continual Learning Neuromorphic Computing

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Spiking neural networks (SNNs) promise energy-efficient artificial intelligence on neuromorphic hardware but struggle with tasks requiring both fast adaptation and long-term memory, especially in continual learning. We propose Local Timescale Gating (LT-Gate), a neuron model that combines dual time-constant dynamics with an adaptive gating mechanism. Each spiking neuron tracks information on a fast and a slow timescale in parallel, and a learned gate locally adjusts their influence. This design enables individual neurons to preserve slow contextual information while responding to fast signals, addressing the stability-plasticity dilemma. We further introduce a variance-tracking regularization that stabilizes firing activity, inspired by biological homeostasis. Empirically, LT-Gate yields significantly improved accuracy and retention in sequential learning tasks: on a challenging temporal classification benchmark it achieves about 51 percent final accuracy, compared to about 46 percent for a recent Hebbian continual-learning baseline and lower for prior SNN methods. Unlike approaches that require external replay or expensive orthogonalizations, LT-Gate operates with local updates and is fully compatible with neuromorphic hardware. In particular, it leverages features of Intel's Loihi chip (multiple synaptic traces with different decay rates) for on-chip learning. Our results demonstrate that multi-timescale gating can substantially enhance continual learning in SNNs, narrowing the gap between spiking and conventional deep networks on lifelong-learning tasks.

Abstract

Storage-Efficient Continual Learning

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