As neuromorphic systems scale to thousands of near-memory cores, aging-induced permanent faults in neuron-update datapaths become an important obstacle to long-term deployment. Existing online recovery methods typically retire a faulty core and migrate its neurons, along with their weights and membrane states, to healthy cores. This whole-core treatment incurs high recovery traffic and makes recovery depend on scarce destinations; at high utilization, there may be enough surviving compute capacity but insufficient free storage to copy the affected neuron context. This paper presents SpikeRelay, an online recovery framework for diagnosed compute-unit faults. SpikeRelay exploits the fact that, in many neuromorphic cores, the compute datapath, local SRAM, and router are distinct modules: a compute fault need not destroy stored weights and states or disconnect the core from the NoC. Instead of retiring a faulty core and migrating its neuron data, SpikeRelay converts the faulty core into a storage-and-forwarding node while offloading neuron-update computation to a healthy rescue core. This decoupling of storage and computation eliminates recovery-time data migration and greatly reduces spare-SRAM requirements. Consequently, SpikeRelay sustains 100% recovery at 92.2% SRAM utilization and a 50% fault rate, whereas the best baseline achieves only 22.1%.
Figures & tables
Figure 1. Faults are inevitable exactly where recovery has no room to move data. (a) As core count grows, the probability of at least one in-field permanent fault approaches certainty. (b) Most evaluated SNN workloads already run in the high-utilization regime ( ≥ 85%), leaving little spare SRAM for post-fault relocation.
Figure 2. Conventional migration retires the entire faulty core and copies all neuron data to a healthy core, causing capacity bottlenecks at high utilization while abandoning faulty-core SRAM.
Figure 3. Neuron-level impact of a stuck-at-1 fault in the compute-unit ALU. After fault onset, membrane updates diverge, threshold crossings shift, and spike displacement increases over time.
Figure 4. System model and post-fault deployment rebinding. A compute-unit fault disables only computation. SpikeRelay rebinds Tcomp to a healthy rescue core while keeping storage and communication on the faulty core.
Figure 5. Overview of SpikeRelay. Left and middle: recovery configuration constructs the recovered pipeline via rescue-core selection, faulty-core degradation, rescue-core activation, and routing reconfiguration. Right: during online execution, the rescue core accumulates forwarded spikes, reads the state from the faulty core, performs local updates, writes the updated state back, and emits output spikes. Only computation is migrated; weights and states remain on the faulty core.
Figure 6. Recovery success rate vs. fault rate on a 32×32 chip across three real workloads and an extreme Dense-Stress case. SpikeRelay maintains 100% recovery on real workloads, whereas migration-based strategies degrade as utilization increases.
Figure 7. Data migration overhead vs. fault rate across the same four workloads. SpikeRelay incurs zero migration, whereas migration baselines peak and then fall as target capacity is exhausted.
Figure 8. Cycle-accurate recovery latency vs. fault rate across the same four workloads. SpikeRelay completes recovery in only tens of cycles because it sends only constant-size metadata, whereas migration baselines require 104 – 106 cycles due to bulk data movement and NoC contention.
Figure 9. End-to-end inference accuracy on CIFAR10-Conv5 under 0%–50% fault rates. SpikeRelay maintains accuracy, while migration baselines degrade as neuron loss accumulates.
Approach
Data Migr.
Latency
High-Util.
Faulty SRAM
HW Redund.
None
Very low
Limited
Abandoned
Retrain / Adj.
None
Offline
Limited
Abandoned
Data Reloc.
High
High
Limited
Abandoned
SpikeRelay
Zero
Very low
Yes
Retained
Table 1. Qualitative comparison of fault recovery approaches.
The potential for neuromorphic computing to provide intrinsic fault tolerance has long been speculated, but the brain's robustness in neuromorphic applications has yet to be demonstrated. Here, we show that a previously described, natively spiking neuromorphic algorithm for solving partial differential equations is intrinsically tolerant to structural perturbations in the form of ablated neurons and dropped spikes. The tolerance band for these perturbations is large: we find that as many as 32 percent of the neurons and up to 90 percent of the spikes may be entirely dropped before a significant degradation in the accuracy results. Furthermore, this robustness is tunable through structural hyperparameters. This work demonstrates that the specific brain-like inspiration behind the algorithm contributes to a significant degree of robustness expected from brain-like neuromorphic algorithms.
Bradley H. Theilman, James B. Aimone
Neural Exploration & Research Laboratory, Sandia National Laboratories, Albuquerque, NM
Many-core neuromorphic systems accelerate Spiking Neural Networks (SNNs), yet their packet-based spike communication can spend substantial traffic and energy repeatedly transmitting destination addresses. This overhead is amplified by the small payload of spike packets: in representative workloads, duplicate address transmissions account for up to 49% of the total traffic. This paper presents UniSpike, a hardware-software co-design that removes address redundancy by aggregating spikes destined for the same core into compact packets. UniSpike combines destination-centric spike scheduling, lightweight runtime packet assembly hardware, and destination-aware SNN partitioning. Across diverse SNN workloads, UniSpike reduces traffic by 1.93× on average, delivering 1.77× speedup and 1.50× energy efficiency improvement over state-of-the-art designs.
We propose a scalable neuromorphic architecture based on spiking dynamics emerging from the autonomous time-continuous evolution of clockless (asynchronous) digital circuits. Implemented on commercially available field-programmable gate arrays (FPGAs), our system implements networks of interacting Boolean spiking neurons with configurable excitatory and inhibitory synaptic weights. A complete processing pipeline enables efficient handling of spike-encoded data for solving machine-learning tasks. We demonstrate competitive performance for an audio classification task with spike-based encoding and high-speed processing. Power consumption is significantly lower than traditional digital implementations; this makes our approach an efficient alternative that bridges the gap to dedicated analog neuromorphic systems without the need for specialized hardware design. More generally, our approach establishes clockless digital hardware as a viable platform for neuromorphic computing. It paves the way for reconfigurable chips to be turned into energy-efficient quasi-analog neuromorphic processors.
Eric Oliveira Gomes, Damien Rontani
LMOPS UR4423 Laboratory, CentraleSup´elec and Universit´e de Lorraine, Metz F-57070, France