FIGFLEX: A Mixed-Precision FP-INT GEMM Accelerator Co-Designed with Low-Bit LLM Quantization
Organizations: University of California, Irvine, Irvine, CA, USA
Abstract
Weight-only quantization keeps LLM activations in floating point and stores weights as low-bit integers, turning the dominant workload into floating-point-integer (FP-INT) general matrix multiplication. Recent quantizers reach a 2-3-bit average with mixed precision, but hardware has not kept pace: GPUs dequantize weights to FP16 before the tensor-core multiply-accumulate, and bit-parallel FP-INT accelerators run at a single weight precision, so fewer bits save memory but not computation. In this paper, we present FIGFLEX, an algorithm-hardware co-designed mixed-precision accelerator whose bit-parallel datapath scales throughput as precision falls. FIGFLEX contributes (1) a shift-add, radix-4 reformulation of FP-INT multiplication that fuses the multiply-accumulate into a unified, precision-flexible partial-product reduction and roughly halves the partial products, together with a novel INT3 optimization that reclaims the idle datapath radix-4 leaves at that precision; and (2) a mixed-precision quantizer that assigns each channel group its bit-width according to the error GPTQ cannot compensate, with a per-input-channel column scaling whose power-of-two normalization keeps the scaled activations out of the FP16 subnormal range, so that the quantized model maps directly onto FIGFLEX's datapath with the same accuracy as on a GPU. On LLaMA-2-7B, FIGFLEX attains 5.85 and 8.77 WikiText-2 perplexity at 3- and 2-bit average precision, lower than GPTQ, AWQ, SliM-LLM, AMQ, and QuIP# (without fine-tuning), while delivering 1.56x and 1.42x higher whole-chip throughput per area on the linear GEMMs of a 3-bit mixed-precision model than AxCore and FIGLUT, respectively.
Figures & tables
| INT4 (2 lanes/wt) | INT3 (3 lanes/2 wt) | |||
| Lane | mux inputs | digit | mux inputs | digit |
| 1 | ||||
| 2 | ||||
| 3 | ||||
| 4 | ||||
| 5 | ||||
| Point | W4/W3/W2/W1 (%) | Bits | MAC/cycle | INT4 | Util. | |
| F3 | 1/98/1/– | 3.00 | 10.67 | 99.4% | ||
| F2 | –/20/60/20 | 2.00 | 16.0 | 99.0% |
| Design | Key datapath |
| FP FMA | FP mult. align normalize FP acc. |
| Dot-product | FP INT4, per-element normalize FP acc. |
| FIGNA [ 20 ] | shared-exp. align INT mult. INT acc. |
| FIGLUT [ 40 ] | activation LUT read (bit-serial) INT acc. |
| AxCore [ 60 ] | log-approx. mult. partial-FP acc. |
| FIGFLEX | radix-4 mux, no mult. INT acc. |
| L2-7B | L3.1-8B | Q2.5-7B | ||||||||||||||||||||
| Method | Bits | Wiki2 | C4 | PIQA | ARCe | ARCc | HS | Wino | Wiki2 | C4 | PIQA | ARCe | ARCc | HS | Wino | Wiki2 | C4 | PIQA | ARCe | ARCc | HS | Wino |
| FP16 | 16 | 5.47 | 6.97 | 78.1 | 75.5 | 43.0 | 76.2 | 69.2 | 6.24 | 8.95 | 79.1 | 82.2 | 52.1 | 79.3 | 74.5 | 6.85 | 10.44 | 78.8 | 80.4 | 47.8 | 60.0 | 72.9 |
| GPTQ | 3 | 6.14 | 8.05 | 76.0 | 73.1 | 39.0 | 71.9 | 67.6 | 7.74 | 11.95 | 75.5 | 72.8 | 40.2 | 73.9 | 70.7 | 7.69 | 11.77 | 76.9 | 77.1 | 45.9 | 55.8 | 68.1 |
| AWQ | 3 | 6.18 | 7.81 | 76.6 | 74.3 | 40.6 | 54.8 | 68.0 | 8.15 | 11.56 | 76.6 | 76.1 | 45.1 | 56.1 | 70.9 | 8.14 | 11.75 | 77.5 | 79.4 | 46.8 | 56.0 | 69.5 |
| QuIP# | 3 | 6.24 | 7.70 | 76.5 | 74.4 | 41.2 | 53.4 | 69.1 | 7.79 | 10.89 | 77.3 | 75.3 | 43.6 | 56.1 | 70.8 | 7.45 | 11.05 | 78.4 | 80.4 | 48.6 | 56.9 | 72.0 |
| AMQ ‡ | 3.05 | 6.70 | 8.83 | 76.4 | 69.4 | 42.4 | 72.1 | 68.7 | 9.20 | 14.29 | 76.6 | 70.8 | 43.9 | 71.3 | 70.0 | 12.30 | 20.41 | 73.9 | 66.5 | 41.5 | 67.0 | 63.3 |
| WikiText-2 PPL | GEMM latency (ms) | |||
| Configuration | 3-bit | 2-bit | 3-bit | 2-bit |
| GPTQ (official, act-order) | 7.744 | 98.94 | 654.3 | 436.2 |
| Tuned uniform (col. scaling) | 7.227 | 29.28 | 666.9 | 448.8 |
| CA-Mixed, no col. scaling | 7.370 | 16.48 | 658.3 | 440.6 |
| SBA-Mixed + col. scaling [ 19 ] | 7.237 | 18.84 | 670.8 | 453.2 |
| CA-Mixed + col. scaling (ours) | 7.193 | 13.77 | 670.8 | 453.2 |
| Datapath | Op. | PE | Repl. | m 2 / | mW/ | INT3 |
| ( m 2 ) | ( m 2 ) | MAC | MAC | MAC/cyc. | ||
| Radix-2 tree | 1 | 1144 | 12.9 | 144.6 | 0.167 | 10.67 |
| Radix-4 | 3 | 873 | 12.7 | 110.8 | 0.162 | 8 |
| Radix-4+INT3 | 3 | 881 | 16.3 | 112.2 | 0.165 | 10.67 |
| Radix-8 | 7 | 911 | 21.3 | 116.6 | 0.168 | 10.67 |
| Radix-16 | 15 | 1239 | 30.7 | 158.7 | 0.201 | 10.67 |
| Area | Power (W) | TOPS | Request (s) | ||||
| Design | (mm 2 ) | chip | +HBM | F3 | F2 | F3 | F2 |
| FP FMA | 11.10 | 17.52 | 20.17 | 32.8 | 32.8 | 4.58 | 4.39 |
| Dot-product | 9.52 | 9.59 | 12.24 | 32.8 | 32.8 | 4.58 | 4.39 |
| FIGNA [ 20 ] | 5.11 | 5.04 | 7.69 | 32.8 | 32.8 | 4.58 | 4.39 |
| FIGLUT [ 40 ] | 4.68 | 5.22 | 7.87 | 43.7 | 65.5 | 3.70 | 2.65 |
| AxCore [ 60 ] | 3.97 | 5.02 | 7.67 | 32.8 | 32.8 | 4.58 | 4.39 |
LLM Inference Acceleration
LLM inference acceleration develops algorithms and systems that reduce language-model latency, memory use, and serving cost while preserving output quality.
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