NN-Based Transistor Modeling for Ultra-Fast SPICE Simulation and Standard Cell Library Characterization

Rodion Novkin; Hussam Amrouch

cs.ETOct 22, 2026

NN-Based Transistor Modeling for Ultra-Fast SPICE Simulation and Standard Cell Library Characterization

Authors: Rodion Novkin, Hussam Amrouch

Organizations: Technical University of Munich; TUM School of Computation, Information and Technology; Chair of AI Processor Design; Munich Institute of Robotics and Machine Intelligence, Munich, Germany

Abstract

Neural network (NN)-based transistor models have proven to be a promising solution to accelerate device modeling. Although these models demonstrated remarkable speedup in circuit simulations, they were not rigorously tested in complex tasks within standard EDA tool flows for chip design, which require very high transistor model precision to provide accurate results and converge properly. To investigate their full potential and promise, we develop NN-based transistor models that accurately predict the drain current and various charges for a 3nm nanosheet, and employ the models for a standard cell library characterization. This enables us to evaluate the accuracy and speedup under a very wide range of SPICE simulations, benchmarking our models against an industry-standard implementation. Since standard cell library characterization involves thousands of SPICE simulations, it serves as a great benchmark for transistor model quality and consistency. To further evaluate model accuracy, we also perform analog- and digital-level simulations for various complex circuits. Our experiments reveal that NN-based models are a valid alternative to existing transistor compact models, capable of producing accurate delay and power estimates with a much higher speed and convergence time compared to the conventional Verilog-A-based industry-standard (BSIM-CMG) transistor compact model. Our NNs achieve sub-0.11% and 0.76% errors for delay and total power evaluation on a wide range of circuits, while taking up to 8 times less time during the standard cell library characterization. Additionally, we provide comprehensive information and guidance on NN accuracy, unveiling the relationship between NN size and its effect on circuit simulation precision.

Figures & tables

Fig. 1 : NN-based transistor model is implemented in Verilog-A out of pre-trained networks. Then, all transistor models are employed for the standard cell library characterization, and the output libraries are used for timing and power signoff estimation and compared to the industry-standard BSIM-CMG.

Abbreviation	Description	Cells
Norm	Normalization for Fractional Input	70
CRC	Cyclic Redundancy Check	150
Adder128	128-bit Adder	194
InvSqrtFP	Floating-Point Reciprocal of Square Root	1271
ExpFP	Floating-Point Exponential	4214
SinCosFP	Floating-Point Sine or Cosine	5017

TABLE I : Circuits used for timing and power signoff estimation.

Panel of Figure 3 — Fig. 2 : NN8 model exhibits an excellent fit for nMOS and pMOS transconductance and output conductance. Lines are NN8 outputs, similar-colored dashed lines - BSIM-CMG industry-standard compact model. Either $V_{\text{G}}$ or $V_{\text{D}}$ is fixed, depending on the plot. Y-scale is the same for nMOS (right) and pMOS (left) plots.

Panel of Figure 4 — Fig. 3 : NN8 model demonstrates a good fit for capacitances in necessary regions. Lines are NN8 outputs, similar-colored dashed lines - BSIM-CMG industry-standard compact model. Either $V_{\text{G}}$ or $V_{\text{D}}$ is fixed, depending on the plot. Y-scale is the same for nMOS (right) and pMOS (left) plots.

Variable	nMOS				pMOS
	NN16		NN8		NN16		NN8
	RMSE	MAPE	RMSE	MAPE	RMSE	MAPE	RMSE	MAPE
$I_{\text{D}}$	0.026 $\mathrm{\SIUnitSymbolMicro A}$	0.32 $\%$	0.056 $\mathrm{\SIUnitSymbolMicro A}$	0.73 $\%$	0.037 $\mathrm{\SIUnitSymbolMicro A}$	0.51 $\%$	0.072 $\mathrm{\SIUnitSymbolMicro A}$	0.59 $\%$
$g_{m}$	0.290 $\mathrm{\SIUnitSymbolMicro S}$	2.54 $\%$	0.914 $\mathrm{\SIUnitSymbolMicro S}$	8.84 $\%$	0.369 $\mathrm{\SIUnitSymbolMicro S}$	0.89 $\%$	0.553 $\mathrm{\SIUnitSymbolMicro S}$	1.03 $\%$
$g_{DS}$	0.677 $\mathrm{\SIUnitSymbolMicro S}$	4.28 $\%$	1.256 $\mathrm{\SIUnitSymbolMicro S}$	8.54 $\%$	0.737 $\mathrm{\SIUnitSymbolMicro S}$	4.42 $\%$	1.077 $\mathrm{\SIUnitSymbolMicro S}$	7.54 $\%$
$Q_{\text{D}}$	0.007 $\mathrm{a}\mathrm{C}$	0.22 $\%$	0.011 $\mathrm{a}\mathrm{C}$	0.29 $\%$	0.041 $\mathrm{a}\mathrm{C}$	3.84 $\%$	0.036 $\mathrm{a}\mathrm{C}$	1.93 $\%$

TABLE II : Prediction error of trained neural networks.

Fig. 4 : 16-bit divider circuit containing 5270 transistors. Simulation with NN8 model and a low-precision simulation (LPS) setup shows an excellent visual match with BSIM-CMG simulated with the default precision setup. D1-D4 indicate the points for delay measurement for the output voltage at quotient_0 node with respect to the input a_0 .

V_{dd}

0.7\text{\,}\mathrm{V}

Fig. 5 : 1001-stage NAND ring oscillator (RO) circuit containing 4004 transistors. Simulation with NN8 model and a low-precision simulation (LPS) setup shows minor visual deviations with BSIM-CMG and NN8 simulated with the default precision setup.

V_{dd}

0.7\text{\,}\mathrm{V}

Divider	BSIM-CMG	NN16		NN8		NN8 (LPS)
delay point	Delay [ $\mathrm{p}\mathrm{s}$ ]	Delay [ $\mathrm{p}\mathrm{s}$ ]	RE [%]	Delay [ $\mathrm{p}\mathrm{s}$ ]	RE [%]	Delay [ $\mathrm{p}\mathrm{s}$ ]	RE [%]
D1	296.00	295.93	-0.024	295.66	-0.115	295.37	-0.213
D2	216.00	216.07	+0.032	216.06	+0.028	215.93	-0.032
D3	91.40	91.41	+0.011	91.29	-0.120	91.19	-0.230
D4	51.10	51.07	-0.059	50.99	-0.215	50.77	-0.646
RO period [ps]	12720	12732	+0.094	12734	+0.110	12752	+0.252

TABLE III : Delay measurements for the 16-bit divider for delay points shown in Fig. 4 and 1001-stage NAND ring oscillator (RO) period measurements. Relative error (RE) is calculated with respect to BSIM-CMG.

	16-bit divider				1001-stage NAND RO
Model	Time	Iterations		Computational	Time	Iterations		Computational
Model	[s]	Total	Converged	throughput [iter/s]	[s]	Total	Converged	throughput [iter/s]
BSIM-CMG	1573	29609	16198	18.82	5165	139191	70313	27
NN16	657	33635	20087	51.19	146	156789	88929	1074
NN8	272	33518	20016	123.23	130	149391	86996	1149
BSIM-CMG (LPS)	794	20094	6383	25.31	2615	89584	28380	34.3

TABLE IV : Time and number of iterations required for the 16-bit divider and 1001-stage NAND ring oscillator (RO) simulations.

Panel of Figure 10 — Fig. 6 : Relative simulation time reduction for NN-based transistor models compared to BSIM-CMG. All relative values are calculated using data from Table IV .

Panel of Figure 11 — Fig. 7 : Relative error for circuit delay estimation calculated with respect to BSIM-CMG for different supply voltages.

Panel of Figure 12 — Fig. 8 : Distribution of relative errors for standard cell delays measured with respect to the BSIM-CMG. $V_{dd}$ = $0.8\text{\,}\mathrm{V}$ . NN16 model demonstrates marginally better results over NN8 model. Standard cell library characterization performed with low-precision simulations shows significant deviations from the reference.

Circuit	BSIM-CMG	NN16		NN8		NN8 (LPS)
Circuit	Delay $[ns]$	Delay $[ns]$	RE [%]	Delay $[ns]$	RE [%]	Delay $[ns]$	RE [%]
CRC	0.343551	0.343626	+0.022	0.343756	+0.060	0.341851	-0.495
ExpFP	3.177209	3.179308	+0.066	3.180068	+0.090	3.172469	-0.149
MAC32	2.179060	2.181101	+0.094	2.183413	+0.200	2.176965	-0.096
Div64	8.563543	8.568236	+0.055	8.564155	+0.007	8.540630	-0.268
Exp64	8.669079	8.675332	+0.072	8.670883	+0.021	8.739084	+0.808

TABLE V : Static timing analysis. Relative error (RE) is calculated with respect to BSIM-CMG.

V_{dd}

0.8\text{\,}\mathrm{V}

Panel of Figure 14 — Fig. 9 : NN-based transistor models show a significant reduction in time required for standard cell library characterization, with NN16 being approximately $8\times$ faster than BSIM-CMG.

Circuit	Net switching power		Cell internal power		Cell leakage power		Total power
Circuit	Value [W]	RE [%]	Value [W]	RE [%]	Value [W]	RE [%]	Value [W]	RE [%]
CRC	7.032e-05	-0.043	4.395e-05	+0.023	1.251e-07	+0.160	1.144e-04	+0.000
ExpFP	1.664e-04	+0.000	1.570e-04	+0.512	3.811e-06	+0.184	3.271e-04	+0.214
MAC32	5.252e-04	+0.019	7.313e-04	+0.647	9.299e-06	+0.216	1.266e-03	+0.397
Div64	6.088e-04	-0.033	4.116e-04	+0.195	3.661e-05	+0.192	1.057e-03	+0.095
Exp64	2.079e-03	+0.000	1.406e-03	+0.214	3.653e-05	+0.192	3.521e-03	+0.057

TABLE VI : Circuit power analysis with NN-based transistor model. Absolute values are given for NN16, and relative errors (RE) are calculated with respect to BSIM-CMG.

Panel of Figure 16 — Fig. 10 : Distribution of relative errors for cell internal power measured with respect to the BSIM-CMG. $V_{dd}$ = $0.8\text{\,}\mathrm{V}$ . NN8 error distribution looks visually similar to the NN16 one. However, the average error for NN16 is lower than that for NN8 due to higher accuracy.

Neural Surrogate Modeling

Neural surrogate modeling uses learned models to approximate costly simulations, enabling faster prediction, design, control, and inference.

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PRISM-UDE: Physics-Regularized Iterative Symbolic Modeling of 3nm FinFETs via Universal Differential Equation

Pranavanath Balamurali, Prathamesh Dinesh Joshi, Raj Abhijit Dandekar, Rajat Dandekar+1

The University of Texas at Austin · Vizuara AI Labs

Physics-Informed ML Neural Surrogate Modeling

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Compact transistor models are the mathematical backbone of circuit simulation. However, at advanced nodes such as 3nm, transport physics becomes too complex for traditional hand-derived equations to capture accurately. Purely data-driven neural surrogates, on the other hand, are numerically unstable inside circuit solvers and offer no physical insight into their own predictions. We introduce PRISM-UDE (Physics-Regularized Iterative Symbolic Modeling via Universal Differential Equations), a framework that embeds a small neural network inside a physics-based transistor model, using the network only to learn the transport behavior that the analytical baseline misses, rather than replacing the physics altogether. Once trained, this neural correction is distilled into a single, interpretable closed-form expression via symbolic regression, making the final model fully analytical and simulator-ready. Applied to a 3nm FinFET benchmark dataset, PRISM-UDE reduces prediction error more than sixfold (70.33% to 11.01%) relative to the standard physics-only baseline. The distilled expression preserves this accuracy almost exactly while eliminating the neural network entirely. We further validate the extracted expression directly inside a SPICE circuit simulator, confirming stable, physically consistent behavior under both static bias sweeps and dynamic switching conditions.

Abstract

Neural Surrogate Modeling

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