cs.NEOct 23, 2026

A Resource-Efficient and Precision-Scalable FPGA Accelerator for Spiking Neural Networks Using Minifloat Arithmetic

Authors: Ali Mehrabi, Philip C. Jose

Organizations: School of Engineering, Computing, and Science, Western Sydney University, Sydney, Australia

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Abstract

Spiking neural networks (SNNs) are well suited to event-driven edge intelligence, but the arithmetic complexity, memory footprint, and power consumption associated with conventional floating-point implementations can limit their deployment on resource-constrained hardware. This paper presents a precision-scalable and resource-efficient SNN hardware accelerator architecture based on parameterized minifloat arithmetic. The proposed architecture implements recurrent leaky integrate-and-fire (LIF) neurons and leaky-integrator (LI) readout neurons using a unified minifloat datapath whose word length and mantissa width can be configured at synthesis time. A valid-driven arithmetic subsystem employs pipelined minifloat multiplication and addition, while time-multiplexed processing enables arithmetic resources to be shared across synaptic accumulation, neuron-state updates, recurrent connections, and output processing. This organization reduces replicated arithmetic hardware and provides a scalable design approach for different SNN sizes and precision requirements. The architecture supports E8M23, E5M10, E5M6, and E4M3 formats within the same RTL framework, allowing precision, memory capacity, timing, and power to be traded without modifying the underlying neuron architecture. FPGA implementation results demonstrate that reducing minifloat precision substantially decreases arithmetic-resource utilization and estimated dynamic power, while also reducing the theoretical storage requirement of synaptic parameters. A recurrent event-based classification network is used as a hardware validation case, demonstrating that substantial precision reduction can be achieved while retaining competitive inference accuracy. The results establish parameterized minifloat computation as an effective basis for scalable, low-resource, and energy-efficient FPGA SNN accelerators.

Figures & tables

Fig. 1: Generic architecture of the precision-scalable SNN accelerator. Network topology, parameters, and numerical precision are configurable.
FormatNNSignEEMM
E8M23321823
E5M10161510
E5M612156
E4M38143
TABLE I: Evaluated Numerical Formats
Fig. 2: LIF neuron datapath with parameterized minifloat arithmetic. The block sequence follows the RTL update order, and the shared adder and multiplier are realized as valid-driven pipelined arithmetic units.
FormatFmax⁡F_{\max} (MHz)WNS (ns)CLBsLUTsFFsDSPsBRAM/URAMDynamic Power (W)
E8M23226.6030.58721583990909440/00.298
E5M10256.9371.1087762253481920/00.196
E5M6268.5281.2766651818371720/00.161
E4M3262.6051.1924641339261820/00.147
TABLE II: Post-Route FPGA Comparison on XCU250
FormatRTL AccuracyStorage (KiB)Reduction
E8M2396.30%997.7baseline
E5M1096.30%498.850.0%
E5M696.30%374.162.5%
E4M388.89%249.475.0%
TABLE III: Validation Accuracy and Raw Learned-Weight Storage
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