cs.AROct 30, 2026

TADA: Technology Aware DNN Accelerator Performance and Energy Estimator

Authors: Tanvi Sharma, Surya Selvam, Anand Raghunathan, Kaushik Roy

Organizations: Purdue University, West Lafayette, USA

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Abstract

Deep neural network (DNN) accelerators for edge inference must meet tight energy, latency, and area (EDP) constraints, and their optimal hardware architecture and dataflow configuration is typically identified through design space exploration (DSE). However, on-chip memory technology including cell type, bank organization, and process node, is rarely treated as a first-class citizen in DSE. For example, increasing memory capacity can reduce memory accesses through greater data reuse, but at the cost of higher area and access energy, thereby limiting the compute units budget. Consequently, memory technology can fundamentally shift the optimal accelerator architecture for a given area and EDP budget. Existing machine learning (ML)-based DSE methods require repeating simulation, data generation, and model training for each new memory technology. We present TADA, a memory technology-aware DNN accelerator performance and energy estimator that predicts system latency and energy for a given workload, hardware configuration, and memory technology. TADA is trained on a synthetic dataset that generalizes across memory technologies. The dataset spans current and future technology trends while enforcing physics-based guardrails to preserve realistic area-energy trade-offs. Each memory technology is represented by a technology signature, a vector of read energy, write energy, and storage capacity across a range of areas, provided as input alongside the workload and hardware configuration. Across 21 unseen technology curves spanning SRAM, STTRAM, ReRAM, PCM, FeFET, eDRAM, and CTT, TADA predicts system energy and latency with 1.5-4.4% and 0.7-1.2% mean absolute percentage error, respectively. In three pairwise case studies, it matches the simulator-selected memory technology at 98.7-100% of area budgets, with a mean EDP loss of at most 0.21%, while achieving over 10^4x higher evaluation throughput.

Figures & tables

Figure 1. Best EDP for each technology after jointly optimizing compute array size and buffer capacity at each area budget for a transformer-based prefill workload. Bars are normalized to the best technology at each budget; the dashed line shows that the budget-best EDP decreases as area increases. Grouped bar chart of normalized energy–delay product for each memory technology at several area budgets, with a dashed line showing the best achievable EDP falling as the area budget grows. The lowest-EDP technology changes with budget: eDRAM at 1 mm squared, PCM at 5 mm squared, and SRAM at 16 mm squared.
Figure 2. Area-dependent signatures for 21 evaluation curves, combining CACTI, NVSim/NVMExplorer, and independently characterized inputs ( Muralimanohar et al., 2009 ; Dong et al., 2012 ; Pentecost et al., 2022 ) . Three log-scale plots show read energy, write energy, and capacity versus modeled macro area for 21 evaluation curves.
Figure 3. Overview of TADA. (1) Synthetic technology dataset is created by using real technology for baseline sampling, then perturbed and filtered by physics-aware constraints to form a diverse synthetic corpus; the inset shows representative read-energy, write-energy, and capacity profiles. (2) Each technology signature is combined with a workload and DCIM-array configuration, labeled by ZigZag, and used to train the TADA surrogate. (3) At evaluation, the frozen surrogate estimates energy and latency for unseen technology–workload–hardware candidates and supports iterative area-constrained search; the inset summarizes the energy and latency distribution of the simulator-labeled training corpus. Three-stage flow diagram. Stage one generates synthetic memory technology curves from real reference technologies, perturbs them, and filters them with physics-aware constraints. Stage two combines each technology signature with workload and DCIM array configurations, labels them with the ZigZag simulator, and trains a regression surrogate. Stage three uses the trained surrogate to estimate energy and latency for unseen technologies and to search for the best configuration under an area budget.
TechnologyTotal EnergyTotal Latency
MAPER2R^{2}MAPER2R^{2}
SRAM 6T/8T (22 nm)1.5%0.99960.7%0.9999
SRAM 6T/8T (32 nm)1.5%0.99960.7%0.9999
STTRAM (7 designs)2.8%0.99881.0%0.9999
ReRAM (6 designs)2.8%0.99891.0%0.9999
PCM4.4%0.99800.9%0.9999
Table 1. TADA accuracy on unseen memory technologies. MAPE is computed in linear space and R2R^{2} in log space, consistent with the model target.
Figure 4. Best-EDP configuration versus area budget for STTRAM/ReRAM: (a) simulator, (b) TADA, and (c) EDP loss of TADA’s selection. Three panels plotted against area budget. Panels (a) and (b) show the compute array size and buffer capacity selected by the simulator and by TADA, with background shading marking whether STTRAM or ReRAM is chosen; the two panels closely match. Panel (c) shows TADA's EDP loss, which stays near zero with a maximum of about 1.5 percent.
Figure 5. Best-EDP configuration versus area budget for SRAM8T versus ReRAM: (a) simulator, (b) TADA, and (c) EDP loss of TADA’s selection. Three panels plotted against area budget. Panels (a) and (b) show the compute array size and buffer capacity selected by the simulator and by TADA, with background shading marking whether SRAM8T or ReRAM is chosen; the selected technology alternates five times and TADA reproduces every alternation. Panel (c) shows TADA's EDP loss, averaging 0.21 percent.
Figure 6. Best-EDP configuration versus area budget for ReRAM bank-4 versus bank-16 organizations: (a) simulator, (b) TADA, and (c) EDP loss of TADA’s selection. Three panels plotted against area budget. Panels (a) and (b) show the compute array size and buffer capacity selected by the simulator and by TADA, with background shading marking whether the ReRAM bank-4 or bank-16 organization is chosen; the choice alternates fifteen times and TADA matches it at every budget. Panel (c) shows TADA's EDP loss, averaging 0.18 percent with one spike near 7 percent at a transition budget.
QuantityApple M4EPYC 9334
ZigZag time/config. (s)23.2138.90
TADA time/config. (ms)0.4210.864
Direct speedup5.51×1045.51\times 10^{4}4.50×1044.50\times 10^{4}
Table 2. Direct same-host runtime over 148 matched evaluations; entries are arithmetic means.
Figure 7. Mean absolute SHAP attributions for total energy (a) and total latency (b). Two SHAP feature-importance plots. For total energy (a), sequence length and write energy are the most influential features, followed by hidden dimension, array size, and capacity. For total latency (b), array size and workload shape dominate, with capacity contributing through data reuse.
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