Analog and hybrid computing in the 21st century

Bernd Ulmann; Olivier Bournez; Corey J. Maley; Zhong Sun; Grace Li Zhang; Paul Manea; Michael Döll; Frank Delvigne

math.DSOct 30, 2026

Analog and hybrid computing in the 21st century

Authors: Bernd Ulmann, Olivier Bournez, Corey J. Maley, Zhong Sun, Grace Li Zhang, Paul Manea, Michael Döll, Frank Delvigne,

Organizations: FOM University of Applied Sciences for Economics and Management, 60323 Frankfurt a. M., Germany · anabrid GmbH, 60486 Frankfurt a. M., Germany · LIX, CNRS, Ecole Polytechnique, Institut Polytechnique de Paris, 91120 Palaiseau, France · Department of Philosophy, Purdue University, West Lafayette, IN 47907, United States of America · Institute for Artificial Intelligence, School of Integrated Circuits and Beijing Advanced Innovation Center for Integrated Circuits, Peking University, Beijing 100871, China · Hardware for Artificial Intelligence Group, Technical University of Darmstadt, 64283 Darmstadt, Germany · Peter Grünberg Institut (PGI-14), Forschungszentrum Jülich GmbH, 52068 Aachen, Germany · Department of Computer Science, Darmstadt University of Applied Sciences, 64295 Darmstadt, Germany · Gembloux Agro-Bio Tech, Université de Liège, Gembloux, 5030, Belgium · Division of Biosciences, University College London, London, WC1E 6BT, United Kingdom · Université Paris-Saclay, PROSE, INRAE, Antony, 92160, France · Nordita (Nordic Institute for Theoretical Physics), KTH Royal Institute of Technology, Stockholm University, and Uppsala University, Sweden; Department of Mathematics, Stockholm University, Sweden; Department of Mathematics, University of California, Los Angeles; United States of America; Department of Sociology, University of California, Los Angeles; United States of America; and Santa Fe Institute, United States of America · Université Paris-Cité, CNRS, Integrative Neuroscience and Cognition Center, 75006, Paris, France · Department of Physics, University of California, San Diego, CA 92093, USA · German Aerospace Center (DLR), Institute of Aerodynamics and Flow Technology, 37073 Göttingen, Germany · University of Göttingen, Institute for Numerical and Applied Mathematics, 37073 Göttingen, Germany · Institute of Analogue Circuits and Image Sensors, Universität Siegen, 57076 Siegen, Germany · Faculty of Engineering, Free University of Bozen-Bolzano, 39100 Bozen-Bolzano, Italy · International Research Center of Complexity Sciences, Hangzhou International Innovation Institute, Beihang University, 311115 Hangzhou China · School of Life Science and Technology, University of Electronic Science and Technology of China, 611731 Chengdu, China · Department of Computational Science and Philosophy, Frankfurt School of Finance & Management, 60322 Frankfurt a. M., Germany

Abstract

Analog computers solve problems through physical representations of mathematical variables and relations, often using the dynamics of electronic circuits and their associated signals. Many analog computers directly represent nonlinear dynamical systems; they encode their solutions in the signals that they generate. Although most modern scientific computing relies on digital architectures with inherently discrete-valued representations and algorithmic approaches, the design constraints of such architectures increasingly limit both performance and energy efficiency. Analog systems can circumvent some of these constraints; they execute specific computations very efficiently by mapping them directly onto physical processes using smaller and simpler computing elements than the ones in digital architectures. In this article, we provide an interdisciplinary perspective on modern analog and hybrid (i.e., analog-digital) computing. We discuss how modern scientific computing workflows can leverage analog approaches in various applications, such as in simulating dynamical systems, performing optimization, and enabling more energy-efficient implementations of artificial intelligence.

Figures & tables

Panel of Figure 1 — Figure 1: An analog computer program for solving the ordinary differential equation (ODE) $\dot{x}(t)=-\lambda x(t)$ . The symbol with a triangle and rectangle together denotes an integrator, which performs a continuous-time integration over the sum of its inputs. (In this example, we use only one input.) For technical reasons, integrators perform an implicit sign conversion. The circle on top of the integrator gives its initial condition $x(0)=1$ . For this initial condition and times $t\geq 0$ , the integrator output represents the state $x(t)$ . In the feedback loop, $x(t)$ is multiplied by $\lambda$ and applied to the integrator input.

Panel of Figure 2 — Figure 2: Models of computation and the extended Church–Turing thesis. The Church–Turing thesis states that all reasonable and sufficiently powerful models of computation are equivalent in terms of computability. The effective, or extended, Church–Turing thesis asks whether this equivalence also holds at the complexity level, namely whether such models can simulate one another with at most polynomial overhead. Quantum computation is a possible boundary of this principle. While it does not change what is computable, it may change what is efficiently computable. The analogous question for analog computation is whether it remains within this complexity-level equivalence, or whether it constitutes another boundary of the Church–Turing thesis. In the case of polynomial ODEs, this question can be made precise through the length of trajectories. Polynomial-time computation corresponds to solutions of polynomial ODEs whose trajectories have polynomial length.

Panel of Figure 3 — Figure 3: Analog crossbar circuit for solving the linear system $Ax=b$ using operational-amplifier feedback. The matrix $A$ is encoded in the cross-point conductances. The input vector $-b$ is applied as voltages across input resistors of unit conductance (used for matrix scaling) at the row terminals. The row lines of the crossbar are connected to the inverting inputs of operational amplifiers, which are held at virtual ground at steady state by negative feedback. The amplifier outputs are fed back to the column lines of the crossbar, and the steady-state amplifier output voltages represent the solution vector $x$ . At steady state, Kirchhoff’s current law at each row summing node requires the net current from the crossbar and the input branch to be zero (i.e., $Ax-b=0$ ), yielding $x=A^{-1}b$ for invertible $A$ .

Figure 4: Schematic of biological computing approaches. (a) A single input signal applied to a homogeneous microbial population produces a deterministic output response. (b) Biological noise in heterogeneous populations generates a distribution of outputs across subpopulations. (c) Biological computing approaches range from fully engineered de novo DNA circuits (bottom-up, synthetic biology) to biological substrates of increasing complexity (top-down), spanning abiotic chemical reservoirs, population heterogeneity-based reservoirs, wild-type bacterial reservoirs, and neural/organoid computing systems.

Figure 5: One mREDAC module of the reconfigurable discrete analog computer (REDAC). The individual groups of computing and routing elements are implemented using dual inline memory module (DIMM) form factor elements. A module like this typically contains 24 integrators, 12 multipliers, 96 digitally controlled coefficents, and the necessary switch matrices for automatic reconfiguration under control of a digital computer. Figure courtesy of anabrid GmbH.

Figure 6: Representative computations on the REDAC platform across application classes, each compared against a digital reference solution. All analog data were measured on the physical device. (a) Viscous Burgers equation with a traveling shock. The analog implementation uses $M=32$ interior nodes across four carriers and one hardware integrator per node. We show analog (solid) and the GSL reference (dashed) velocity profiles at five times. The maximum deviation over the full window is $3.8\,\%$ of the unit velocity jump. The inset sweeps the mesh over $M=8$ , $24$ and $32$ . The speed advantage over the processor increases with $M$ , from a factor $3.3$ to a factor $10.3$ . (b) Lorenz attractor ( $\sigma=10$ , $\rho=28$ , $\beta=8/3$ ) in the $x$ – $z$ plane. The Lyapunov exponent fitted to the analog run is $0.909$ . The corresponding literature value is $0.906$ . Analog and digital trajectories decorrelate at $t\approx 0.29$ s, as expected for a chaotic system. (c) Gate-based quantum Fourier transform on three qubits, applied to one full period of a sinusoid across the eight basis states. We show the output-state probabilities against the exact unitary, with mean fidelity $F=0.99992\pm 9.6\times 10^{-6}$ over ten realizations. The transform of that input is a line spectrum of weight $1/2$ at $\ket{100}$ and $\ket{111}$ , and the six states that should be empty carry a total leakage below $10^{-4}$ . (d) Time to solution and energy per run for all four cases. The annotation gives the digital-to-analog ratio. Analog time to solution is the chip op-time and analog energy is a resource-count model, whereas the digital figures are measured wall time and measured RAPL energy. The two energy figures are therefore not like-for-like. The Burgers and quantum Fourier transform op-times were increased to achieve higher accuracy, using coefficient pre-division and a slower integration rate. Therefore, the energy of those two cases is set by the accuracy target rather than by a floor of the hardware. The digital part of the transform is the exact unitary cascade, not an integrated solver, and costs $3.5$ mJ; the same circuit costs $11$ mJ on the qiskit state-vector simulator. The three-qubit transform sits far below the problem size at which the analog route pays off, and is shown to mark that boundary rather than to claim an analog advantage. Figure courtesy of anabrid GmbH.

Figure 7: Prototype chip of a fully reconfigurable analog computer in 65 nm CMOS technology during characterization work in the lab. Figure courtesy of anabrid GmbH.

Figure 8: Overview of the LUCIstack across the problem-space, architecture, and microarchitecture layers. The compiler translates ODE specifications into circuit modules, the runtime manages circuit execution and protobuf-based commands, and the firmware maps these commands to the LUCIDAC hardware through SPI bitstrings. Upward-facing interfaces expose specifications between layers, while downward-facing paths carry compiled modules and runtime messages toward execution.

Figure 9: Solution of the one-dimensional heat equation. Diffusion of an initially Gaussian peak computed on the REDAC platform using 250 spatial nodes and continuous-time integration. Solid orange and dashed black lines indicate the REDAC (analog) and analytical solutions, respectively.

Figure 11: Conceptualization of the concept of “analog supremacy”. The vertical axis is illustrative and indicates typical timescales for digital and analog computing.

Analog Computing

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Jun 11, 2026

Modern analog computing for solving differential and matrix equations

In recent years, driven by the computational demands of data-intensive applications such as artificial intelligence and scientific computing, analog computing has gained renewed interest. Given the diversity of computational tasks and recent advancements in analog CMOS circuits and resistive memory technologies, we refer to the evolving landscape as modern analog computing. In this context, we identify three core computational primitives: solving differential equations, solving matrix equations, and performing matrix-vector multiplications, and we explore the connections among them. We also examine various hardware implementations of these analog computing operators, including those built with discrete components, integrated circuits, and resistive memory devices. Among these, resistive memory arrays emerge as particularly promising due to their implementation efficiency. The paper then surveys recent progress in leveraging modern analog computing to solve differential and matrix equations using both advanced analog CMOS circuits and resistive memory arrays. Finally, we discuss the applications of these circuits, the precision and scalability issues and their potential solutions, the relationship with in-memory computing, and the unique computational complexity of analog computing. This paper provides a unified perspective on analog computing, highlighting its strengths, current developments, and challenges, and positioning it as a pivotal enabler of next-generation computational frontiers.

Zhong Sun, Piergiulio Mannocci, Manuel Le Gallo +1

Institute for Artificial Intelligence, School of Integrated Circuits, Peking University, Beijing Advanced Innovation Center for Integrated Circuits, Beijing 100871, China. · 2Dipartimento di Elettronica, Informazione e Bioingegneria, Politecnico di Milano, Piazza Leonardo da Vinci 32, Milano, 20133, Italy. · 3IBM Research Europe, Rüschlikon, Switzerland.

Analog Computing ODE Solving

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Jun 25, 2026

Generative Models on Analog Hardware with Dynamics

Analog hardware platforms such as coupled oscillators and Analog Ising Machines naturally solve differential equations at a fraction of the energy cost of digital computation, making them attractive for low-power generative modeling, yet a fundamental mismatch exists: modern generative models assume flexible, software-defined dynamics, whereas analog hardware imposes fixed, physics-determined differential equations with limited approximation capacity. This paper introduces Analog Interaction Systems (AIS), a unified framework for hardware-implementable dynamical systems, and empirically characterizes their expressivity gap relative to neural network baselines. Two hardware-compatible mechanisms are proposed to narrow this gap - time-varying piecewise parameters and hidden physical states - and a Wasserstein GAN training procedure is developed to enable training of these models without requiring them to follow a specific trajectory. We characterize how area and power scale with connection density and precision, showing that sparse connectivity and low-bit-width quantized parameters are necessary for practical implementation, and estimate an energy cost of 23uJ per generated image for the chosen architecture, representing a 2-orders-of-magnitude improvement over digital baselines. On MNIST and Fashion-MNIST, our oscillator-based AIS achieves FID scores of 27.6 and 80.8, outperforming the best prior hardware-implementable analog generative models by 3-4x with a 4-bit sparse architecture.

Yu-Neng Wang, Sara Achour

Stanford University · USA

Analog Computing Generative Modeling Generative Adversarial Networks

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Sep 29, 2026

Making Analog Training Scale: Co-Designing Mapping, Optimizer, and Converters

Analog in-memory computing (AIMC) offers an alternative for model training by executing matrix operations directly where weights are stored. However, scaling AIMC to train modern deep models remains an open challenge due to severe hardware non-idealities, including physical weights with finite dynamic range and write granularity, analog-digital converters with finite resolution, and noisy and asymmetric updates. Guided by the insight that gradient accumulation is sensitive to precision and rounding errors, we adopt a mixed-precision training paradigm: executing forward and backward matrix multiplications in the analog domain while computing weight gradients in the digital domain. To enable scalable training, we present a holistic system-algorithm co-design that co-optimizes weight mapping to ensure well-conditioned physical and logical weight profiles, couples a preconditioned optimizer with threshold-triggered open-loop pulsing to stabilize training trajectories, and aligns converter dynamic ranges to suppress quantization errors. Evaluated via hardware-calibrated architectural simulations calibrated with electrochemical RAM measurements, our framework scales Transformer training up to

123\text{M}

parameters with validation loss scaling as

L\propto N^{-0.231}

, where

N

is the parameter count, comparable to

L\propto N^{-0.238}

for digital training.

Zhaoxian Wu, Tayfun Gokmen, Omobayode Fagbohungbe +2

Cornell Tech and Cornell University · IBM T. J. Watson Research Center · Sandia National Laboratories

Mixed-Precision Training Analog Computing Compute-in-Memory Deep Learning Optimization

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Abstract

Analog Computing

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Modern analog computing for solving differential and matrix equations

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