Formal Hardware Verification

The field develops methods to prove that hardware designs meet their specifications, find design bugs, and establish equivalence between implementations. Core techniques include bounded model checking, IC3, SMT-based reasoning, abstraction and refinement, and checking SystemVerilog assertions. Current work also uses learned models and LLM-based agents to generate properties, guide searches, close coverage gaps, and repair RTL, with evaluation on suites such as HWMCC and RTL assertion benchmarks. A central challenge is ensuring that generated properties reflect design intent: syntax and tool acceptance alone do not guarantee meaningful proofs, broad coverage, or reliable bug detection.