Hardware-Software Co-Design

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Hardware-software co-design studies how to shape algorithms, software, and hardware together so a complete system meets goals such as low latency, energy efficiency, or limited memory. Common approaches include quantization and pruning, workload-aware mapping and scheduling, specialized dataflows and accelerators, and joint design of sensors, robots, or other physical systems. Designers explore trade-offs with analytical models, simulators, synthesis tools, and increasingly hardware feedback or AI agents, then evaluate on workloads and deployment platforms. A central challenge is finding designs that remain effective across real workloads and hardware while keeping models, benchmarks, and physical validation reliable.

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69 papers9 papers in the last four weeks, against 1 the four weeks before. 0.1% of all new papers.

ChroNoC: A Tableless TDM Circuit-Switched NoC With Delay-Aware Deployment for Time-Sensitive Neuromorphic Computing
Oct 25, 2026Mohammad Rasoul Roshanshah, Mehdi Modarressi, Saeed SafariNeuromorphic Computing Neural Network Hardware Acceleration
The authors are with the School of Electrical and Computer Engineering, College of Engineering, University of Tehran, Tehran, Iran.
Toward Agentic AI for the 6G Physical Layer: From Algorithm Discovery to Verified Baseband Silicon
Oct 20, 2026Eric Mittag, Lukas Brechtel, Maximilian Stark +1Hardware-Software Co-Design 6G Networks
German Research Center for Artificial Intelligence (DFKI), Kaiserslautern, Germany · CTO System Innovation, NXP Semiconductors, Hamburg, Germany · RPTU University Kaiserslautern-Landau, Germany
Architecting for Hardware Diversity: Meta's End-to-End Co-Design for High-Performance AI Training on AMD GPUs
Oct 15, 2026Haoyu Zhang, Arshad Rahman, Adnan Aziz +55Hardware-Software Co-Design Heterogeneous Computing
C2Flight: A Closed-Loop Co-Simulation Framework for Early-Stage Evaluation of Heterogeneous UAV Computing Systems
Oct 10, 2026Xizhu Chen, Shuyuan Zhang, Yixuan Li +4Heterogeneous Computing Hardware-Software Co-Design
DynaTE: Accelerating Diffusion LLMs via Dynamic Token Execution
Oct 8, 2026Minghan Jiang, Jiayi Wang, Shuaiting Li +2AI Accelerator Inference Diffusion Language Model Inference
College of Information Science & Electronic Engineering, Zhejiang University, Hangzhou 310027, China
Agentic Design Space Exploration for Joint Hardware Configuration Selection and Mapping of AI Inference Workloads on Heterogeneous Edge SoCs
Oct 5, 2026Geetha Prasuna Yarramneni, Surya Selvam, Wilfried Haensch +1Hardware-Software Co-Design Electronic Design Automation
Elmore Family School of ECE, Purdue University, West Lafayette, IN, USA · Pritzker School of Molecular Engineering, University of Chicago, Chicago, IL, USA · Argonne National Laboratory, Argonne, IL, USA
ArtifactArena: Evaluating Models by What They Build in the Physical World
Oct 5, 2026Kushagra Tiwary, David Mayo, Nikhil Behari +5Robotics Simulation Robotics
InfoLab, MIT CSAIL · Camera Culture, MIT Media Lab · Department of Psychiatry, NYU Grossman School of Medicine +1
SparseCraft: Agentic Hardware-Software Co-Optimization for Sparse Computing
Oct 4, 2026Rajatabha Chakraborty, M P Samartha, Vedant Pahariya +1Efficient Neural Network Inference Large Language Model-Guided Optimization
International Institute of Information Technology, Hyderabad, India
Coco: An Agentic Copilot for the Hardware--Software Co-Design Lifecycle
Oct 1, 2026Samuel Kushnir, Kavya Sreedhar, Yeshwanth Reddy Pogula +8Hardware-Software Co-Design LLM Agents
Google DeepMind · Google · MIT
Faster Than Flash: Exploiting Attention Sparsity for Efficient Long-Context Decoding
Aug 31, 2026Zhigeng Liu, Zhiyuan Ning, Ruixiao Li +5Long-Context Language Model Inference LLM Inference Acceleration
Fudan University, Shanghai, China · Shanghai Innovation Institute, Shanghai, China · Harbin Institute of Technology, Harbin, China
Gen-TAS: A Generative AI-Aided Hardware-Software Task Allocation Framework for FPGA-GPP Heterogeneous Systems
Aug 28, 2026Mary Kong, Yuqin Zhao, Semih Vazgecen +2Heterogeneous Computing Hardware-Software Co-Design
Centre for Electronics Frontiers, Institute for Integrated Micro and Nano Systems, School of Engineering, University of Edinburgh, UK
Vision-centric generative AI models: A software-hardware perspective
Aug 27, 2026Eleni Tselepi, Cristian Sestito, Shady Agwa +1Generative Modeling Hardware-Software Co-Design
Centre for Electronics Frontiers, Institute for Integrated Micro and Nano Systems, School of Engineering, The University of Edinburgh, UK
Redwood: A Frontier AI Accelerator Designed, Verified, and Deployed from Scratch in 2 Weeks by AI
Aug 26, 2026Architect LabsAI Accelerator Inference Neural Network Hardware Acceleration
Architect Labs Team* Palo Alto, California
AutoQuREO: A Framework for Automated Quantum Resource Estimation and Optimization
Aug 13, 2026Harshkumar Oza, Aritra Sarkar, Syed Naqi Abbas +4Hardware-Software Co-Design
Quantum Lab, Fujitsu Research of India
Compute-Optimal Is Not Cluster-Optimal: Systems-Aware Scaling for Sparse Mixture-of-Experts
Aug 11, 2026Soumajyoti Sarkar, Yuxin Tang, Sheng ZhaMixture-of-Experts Language Models Language Model Scaling Laws
Amazon AGI Foundations
DIY e-HandPan: A new DIY Low-Cost Handpan Interface based on Arduino and ESP32 Microcontrollers
Aug 10, 2026Benoit Collin, Dominique Fourer, Eric GenotelleHardware-Software Co-Design
IBISC, University of Évry Paris-Saclay
MiCoPro: End-to-End Mixed Precision HW/SW Co-design with HW-aware Proxy Model
Aug 7, 2026Zijun Jiang, Yangdi LyuMixed-Precision Quantization Efficient Neural Network Inference
Microelectronics Thrust, the Hong Kong University of Science and Technology (Guangzhou), Guangzhou 511453, China
Hardware-Software Co-Design for Float16 On-Device Training on RISC-V Single-Core
Jul 23, 2026Benjamin Hubinet, Pierre-Alain Moellic, Olivier Savry +2On-Device Training Hardware-Software Co-Design
CEA-Leti, Mines Saint-Etienne, Equipe Commune SAS, F-13541 Gardanne, France · Univ. Grenoble Alpes, CEA-Leti, F-38000 Grenoble, France · Mines Saint-Etienne, CEA-Leti, Centre CMP, Equipe commune SAS, F-13541 Gardanne, France
ExaGEMM: Exploration Framework for CPU-Driven ML Inference via Associative In-Register Computing for Low-Bit GEMM
Jul 16, 2026Hyunwoo Oh, Suyeon Jang, Hanning Chen +3Efficient Neural Network Inference Hardware-Software Co-Design
University of California, Irvine
Kaleido: Algorithm-Hardware Co-Design for Video Diffusion Transformers by Exploiting Latent Space Correlations
Jul 15, 2026Wenxuan Miao, Haosong Liu, Weiming Hu +9Video Diffusion Models Diffusion Transformer
Shanghai Jiao Tong University · Shanghai Jiao Tong University, Shanghai Qi Zhi Institute · Huawei Technologies +1
Automatic Model-Hardware Co-Adaptation for Heterogeneous AI Accelerators
Jul 14, 2026Tian Chen, Mingheng Mi, Pu Wang +2AI Accelerator Inference LLM Inference
Pazhou Laboratory (Huangpu) · Unaffiliated
A Survey on the Green Development of Large Models: From Resource-Efficient Architectures to Hardware-Software Co-Design
Jul 10, 2026Linhui Xiao, Guiping Cao, Mingyue Guo +6LLM Compression Energy-Efficient ML
1. Pengcheng Laboratory, Shenzhen 518066, China · 2. Harbin Institute of Technology (Shenzhen), Shenzhen 518055, China · 3. Peking University, Beijing 100080, China
Hardware-Enforced Semantic Coordination for Safety-Critical Real-Time Autonomous Systems
Jul 2, 2026Uwe M. Borghoff, Paolo Bottoni, Remo PareschiMulti-Agent Coordination Safety-Critical Control
Department of Computer Science University of the Bundeswehr Munich Neubiberg, Germany · Department of Computer Science Sapienza University of Rome Rome, Italy · STAKE Lab University of Molise Campobasso, Italy
AgRefactor: Self-Evolving Agentic Workflow for HLS Compatibility and Performance
Jun 29, 2026Yang Zou, Zijian Ding, Yizhou Sun +1Multi-Agent LLM Systems LLM Agent Self-Improvement
1Carnegie Mellon University · University of California, Los Angeles
MLSYSIM: First-Principles Infrastructure Modeling for Machine Learning Systems
Jun 28, 2026Vijay Janapa ReddiHardware-Software Co-Design
Harvard University
Co-Optimization of Analog Kolmogorov-Arnold Networks for Low-Power Function Approximation in Flexible Electronics
Jun 26, 2026Paula Carolina Lozano Duarte, Georgios Zervakis, Mehdi Tahoori +1Energy-Efficient ML Kolmogorov-Arnold Networks
Dept. of Computer Science, Karlsruhe Institute of Technology, Karlsruhe 76131, Germany · School of Electrical and Computer Engineering, National Technical University of Athens, Greece · Radyalis LLC, USA
Evidence-Driven LLM Agent for C-to-Synthesizable-C Conversion and Verification
Jun 25, 2026Zhe Zhao, Hongbing Lang, Zhihan Xiao +3Automated Program Repair Code Generation
Shenzhen International Graduate School, Tsinghua University, Shenzhen 518055, China · Shenzhen Belon Technology Co., Ltd., Shenzhen 518055, China
Agentic evolution of physically constrained foundation models
Jun 24, 2026Jiangwei Zhang, Wen Sun, Chong Wang +7Model Compression LLM Quantization
State Key Laboratory of Cyberspace Security Defense, Institute of Information Engineering, Chinese Academy of Sciences, Beijing, 100084, China. · University of Chinese Academy of Sciences, Beijing, 101408, China. · Department of Electronic Engineering, Tsinghua University, Beijing, 100084, China.
Beyond Bayer: Task-Optimal Sensor Co-Design for Robust Autonomous-Driving Segmentation
Jun 23, 2026Reeshad Khan, John GauchAutonomous Driving Perception Computational Imaging
University Of Arkansas, Fayetteville AR 72701, USA
AgentDSE: Reasoning-Augmented Architectural Design Space Exploration
Jun 20, 2026Chenyu Wang, Jiahe Caroline Shi, David Kong +4Large Language Model-Guided Optimization Electronic Design Automation
Harvard University · Massachusetts Institute of Technology · Columbia University

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ChroNoC: A Tableless TDM Circuit-Switched NoC With Delay-Aware Deployment for Time-Sensitive Neuromorphic Computing

Mohammad Rasoul Roshanshah, Mehdi Modarressi, Saeed Safari

The authors are with the School of Electrical and Computer Engineering, College of Engineering, University of Tehran, Tehran, Iran.

Neuromorphic Computing Neural Network Hardware Acceleration Hardware-Software Co-Design Spiking Neural Networks

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Time-sensitive neuromorphic architectures require predictable interconnects to preserve precise event timing. Statically scheduled time-division-multiplexed (TDM) circuit-switched networks-on-chip (NoCs) provide deterministic latency at the cost of linear configuration-memory scaling with schedule depth. Furthermore, jointly optimizing task placement, routing, and scheduling creates an intractable combinatorial search space. Existing deployment frameworks also ignore algorithmic axonal delays by forcing immediate spike injections that increase network contention. This paper proposes a hardware-software co-design to address these challenges. ChroNoC is a tableless TDM NoC that embeds precomputed full-grid broadcast trees into combinational logic as a fixed routing substrate. This fixed substrate reduces deployment to a spatial search via Delay-Aware Reservations and Spatial Annealing (DARSA). DARSA converts axonal delays into periodic scheduling slack to stagger network injections and reduce communication overhead. In a 130nm CMOS process, ChroNoC reduces per-hop energy consumption by more than 75% relative to the evaluated circuit- and packet-switched baselines. On UCI-HAR and N-MNIST workloads, DARSA reduces per-timestep communication cycles by approximately 60% and 45%, respectively, compared with immediate transmission, while also reducing provisioned communication memory. These results demonstrate how combining lightweight TDM switch design with delay-aware deployment improves both hardware efficiency and system-level communication performance while preserving neural event timing.