FPGA-Based Neural Network Acceleration

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The field studies how to map neural-network inference and training onto reconfigurable FPGA logic for edge and real-time systems with tight power or latency limits. Common approaches combine quantization and pruning with pipelined dataflow, systolic or time-multiplexed compute, and high-level synthesis tools such as FINN and hls4ml; LUT-native and event-driven designs target workloads suited to FPGA primitives. Work spans CNNs, transformers, graph networks, and spiking neural networks, using techniques such as sparse execution, on-chip memory reuse, and heterogeneous FPGA systems. The central challenge is balancing accuracy and predictable end-to-end latency against limited logic, compute, memory bandwidth, and energy, while ensuring results hold across devices and deployment conditions.

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Apr 22, 2025

FPGA-Based Neural Network Accelerators for Space Applications: A Survey

Space missions are becoming increasingly ambitious, necessitating high-performance onboard spacecraft computing systems. In response, field-programmable gate arrays (FPGAs) have garnered significant interest due to their flexibility, cost-effectiveness, and radiation tolerance potential. Concurrently, neural networks (NNs) are being recognized for their capability to execute space mission tasks such as autonomous operations, sensor data analysis, and data compression. This survey serves as a valuable resource for researchers aiming to implement FPGA-based NN accelerators in space applications. By analyzing existing literature, identifying trends and gaps, and proposing future research directions, this work highlights the potential of these accelerators to enhance onboard computing systems.

Pedro Antunes, Artur Podobas

FPGA-Based Neural Network Acceleration FPGA Acceleration

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