FPGA Acceleration

FPGA: Field-Programmable Gate Array

FPGA acceleration studies how to map computation onto field-programmable gate arrays, reconfigurable chips used for tasks such as neural-network inference, image and event processing, signal analysis, and real-time control. Common techniques include pipelining and parallel dataflow, fixed-point quantization, memory-local designs, and dividing workloads between FPGAs and CPUs or GPUs. Design tools, high-level synthesis, and emerging AI-assisted methods aim to automate the search for effective hardware architectures. A central challenge is balancing speed and energy use against limited logic and memory, while preserving accuracy and accounting for data movement and implementation reliability.

Latest papers

32 papers3 papers in the last four weeks, against 2 the four weeks before. 0.0% of all new papers.

Decode Late, Multiply Once: Rethinking the Dot Product for Quantized Weights
Oct 22, 2026Jonathan TapsonNeural Network Hardware Acceleration Low-Bit Quantization
BrainChip Inc, Laguna Hills, CA, USA
Reinforcement learning for hardware acceleration and system-level optimization on FPGA and integrated-circuit platforms: A survey
Oct 20, 2026Hamza KheddarGPU-Accelerated RL Reinforcement Learning
LSEA Laboratory, Department of Electrical Engineering, University of Medea, 26000, Algeria
Localization and Neural Splatting on the Edge: An FPGA Scene Memory for Robots
Oct 18, 2026Haohua Que, Mingkai Liu, Tianle Zhu +13DGS Acceleration FPGA Acceleration
School of Environmental, Civil, Agricultural and Mechanical Engineering, College of Engineering, University of Georgia, Athens, GA 30602, USA
SPECTRA: Adaptive Execution of Speculative Decoding on a Runtime-Reconfigurable Tiled Architecture
Sep 21, 2026Gabriele Tombesi, William Baisi, Je Yang +5LLM Inference Acceleration Speculative Decoding
Columbia University New York, USA
AccelMPC: High-Rate, Low-Power FPGA-Accelerated Model Predictive Control for Tiny Drones
Sep 8, 2026Andrea Grillo, Brian PlancherModel Predictive Control Quadrotor Control
Dartmouth College · École Polytechnique Fédérale de Lausanne
Gen-TAS: A Generative AI-Aided Hardware-Software Task Allocation Framework for FPGA-GPP Heterogeneous Systems
Aug 28, 2026Mary Kong, Yuqin Zhao, Semih Vazgecen +2Heterogeneous Computing Hardware-Software Co-Design
Centre for Electronics Frontiers, Institute for Integrated Micro and Nano Systems, School of Engineering, University of Edinburgh, UK
Syn2Logic: End-to-End Neuromorphic Design Automation
Aug 26, 2026Artur PodobasNeuromorphic Computing Electronic Design Automation
Department of Computing and Learning Systems, KTH Royal Institute of Technology, Brinellvägen 8, 100 44 Stockholm, Sweden.
FQTree: Fine-grained Quantization and Hardware Generation of Boosted Decision Trees
Aug 12, 2026Zhiqiang Que, Chang Sun, Haiyang Wang +6Gradient-Boosted Decision Trees Quantization-Aware Training
University of Bristol, UK · California Institute of Technology, USA · Imperial College London, UK
HLSmith: An Expert-Guided Agentic Framework for C/C++-to-HLS Translation
Aug 7, 2026Yuebo Luo, Ahmad Sedigh Baroughi, Philip Stachura +4Code Translation Large Language Model-Guided Optimization
University of Minnesota Twin Cities · Simon Fraser University · Argonne National Laboratory
FinHardBench: Can LLMs Generate Latency-Aware Hardware for Financial Computing?
Aug 2, 2026Weimin Fu, Hejia Zhang, Minghao Shao +6Large Language Model-Guided Optimization Electronic Design Automation
Lehigh University · University of California, San Diego · NYU Tandon School of Engineering +1
Bit-Accurate FPGA Evaluation of Learned Feature Gating in a Fixed-Point Fourier-Feature Automatic Modulation Classifier
Jul 27, 2026Gawthaman Senthilvelan, Luthira AbeykoonAutomatic Modulation Classification FPGA Acceleration
University of Toronto · Toronto, Canada
Classical Hardware Acceleration of Quantum Autoencoders for Real-Time Anomaly Detection in Collider Experiments
Jul 22, 2026Ivan Ge, Sagar Addepalli, Abhilasha Dave +1Online Anomaly Detection Quantum Machine Learning
Department of Physics, Stanford University, 450 Jane Stanford Way, Stanford, 94305, CA, USA. · SLAC National Accelerator Laboratory, 2575 Sand Hill Road, Menlo Park, 94025, CA, USA.
FPGA-Accelerated Neuromorphic Vision System for Real-Time Orbital Object Detection
Jun 17, 2026Diego Hernández, Sebastián Valdivia, Vicente Westerhout +2Event-Based Object Detection FPGA Acceleration
Pontificia Universidad Cat´olica de Valpara´ıso, Valpara´ıso, Chile
Towards Autonomous Accelerator Design: FPGA Accelerator Generation with SECDA
Jun 9, 2026Vinamra Sharma, Xingjian Fu, Jude Haris +1Large Language Model-Guided Optimization Electronic Design Automation
School of Computing Science, University of Glasgow, Scotland, UK
OpenURMA: A Clean-Room Open Implementation of the Unified Bus Protocol
May 27, 2026Bojie LiFPGA Acceleration
Pine AI
EventShiftFlow: Towards Hardware-efficient FPGA-based Flow Estimation
May 27, 2026Arianna Alonso Bizzi, Fernando Cladera, C. J. TaylorOptical Flow Event-Based Vision
University of Pennsylvania, Philadelphia, PA.
SA-Kura: An Energy-Efficient Systolic Array Accelerator for Locally-Coupled Kuramoto Drift in Diffusion Sampling
May 20, 2026Jeongmin Jin, Kyeongwon Lee, Mundo Jeong +2AI Accelerator Inference Diffusion Sampling
ISLPED '26, Evanston, IL
FPGA-Based Hardware Architecture for Contrast Maximization in Event-Based Vision
May 10, 2026Michal Filipkowski, Marcin Kowalczyk, Tomasz KryjakEvent-Based Vision FPGA Acceleration
AGH University of Krakow, Poland Embedded Vision Systems Group, Computer Vision Laboratory
Machine Learning-Based Graph Simplification for Symbolic Accelerators
May 9, 2026Tiffany Yu, Rye Stahle-Smith, Darssan Eswaramoorthi +1FPGA Acceleration
University of South Carolina
Design Conductor 2.0: An agent builds a TurboQuant inference accelerator in 80 hours
May 6, 2026The Verkor Team, Ravi Krishna, Suresh Krishna +1AI Accelerator Inference Multi-Agent LLM Systems
The Verkor Team
Tempus: A Temporally Scalable Resource-Invariant GEMM Streaming Framework for Versal AI Edge
May 1, 2026M. Grailoo, J. Núñez-YáñezLLM Inference Acceleration FPGA Acceleration
∗Linköping University, Sweden · †Universidad Politecnica de Madrid, Spain
Hardware-Efficient FPGA Implementation of Sigmoid Function Using Mixed-Radix Hyperbolic Rotation CORDIC
Apr 26, 2026Chintan Panchal, Ankur Changela, Mohendra RoyFPGA Acceleration
Pandit Deendayal Energy University, Gujarat, India
GraphLeap: Decoupling Graph Construction and Convolution for Vision GNN Acceleration on FPGA
Apr 23, 2026Anvitha Ramachandran, Dhruv Parikh, Viktor PrasannaEfficient Neural Network Inference Dynamic Graph Learning
University of Southern California, Los Angeles, California, USA
ImageHD: Energy-Efficient On-Device Continual Learning of Visual Representations via Hyperdimensional Computing
Apr 23, 2026Jebacyril Arockiaraj, Dhruv Parikh, Viktor PrasannaVisual Representation Learning Energy-Efficient ML
University of Southern California, Los Angeles, CA, USA
AP-DRL: A Synergistic Algorithm-Hardware Framework for Automatic Task Partitioning of Deep Reinforcement Learning on Versal ACAP
Mar 31, 2026Enlai Li, Zhe Lin, Sharad Sinha +1Reinforcement Learning Heterogeneous Computing
The Hong Kong University of Science and Technology, Hong Kong SAR, China · Sun Yat-Sen Univeristy, Guangdong, China · Indian Institute of Technology Goa, Goa, India
Understand and Accelerate Memory Processing Pipeline for Large Language Model Inference
Mar 30, 2026Zifan He, Rui Ma, Yizhou Sun +1LLM Inference LLM Inference Acceleration
Department of Computer Science, University of California, Los Angeles · Microsoft Research Asia
TRINE: A Token-Aware, Runtime-Adaptive FPGA Inference Engine for Multimodal AI
Mar 24, 2026Hyunwoo Oh, Hanning Chen, Sanggeon Yun +5Efficient Multimodal Inference FPGA Acceleration
University of California, Irvine · Purdue University Northwest · Qualcomm +1
SpiderCam: Low-Power Snapshot Depth from Differential Defocus
Mar 18, 2026Marcos A. Ferreira, Tianao Li, John Mamish +4Depth Estimation Computational Imaging
Northwestern University · Georgia Institute of Technology · Purdue University
An FPGA Implementation of Displacement Vector Search for Intra Pattern Copy in JPEG XS
Mar 11, 2026Qiyue Chen, Yao Li, Jie Tao +3FPGA Acceleration
University of Science and Technology of China, Hefei, China
Architectural Design and Performance Analysis of FPGA based AI Accelerators: A Comprehensive Review
Feb 25, 2026Soumita Chatterjee, Sudip Ghosh, Tamal Ghosh +1FPGA Acceleration FPGA-Based Neural Network Acceleration
Indian Institute of Engineering Science and Technology, Shibpur, India

Oct 22, 2026J/K move · Enter open · S save

Decode Late, Multiply Once: Rethinking the Dot Product for Quantized Weights

Jonathan Tapson

BrainChip Inc, Laguna Hills, CA, USA

Neural Network Hardware Acceleration Low-Bit Quantization Quantization FPGA Acceleration

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Large neural networks are increasingly deployed with 1-4 bit weights and 16- or 32-bit activations, yet their dot products still use one multiplier per element. We show that a length-n dot product with k-bit weight codes can be computed with n+2^k additions and at most 2^k decodes and 2^k multiplications. Each weight code is used directly as an address offset that selects one of 2^k accumulators; each activation is added into the selected accumulator; and the accumulated sums are decoded and multiplied only once, at the end, in a fused decode-and-multiply step. The decoded weight vector is never formed. The refactoring is exact for integer arithmetic, works with integer or floating-point operands and with arbitrary, including nonlinear, decoders, and extends to group-wise scales and to matrix and tensor products. The multiplier count falls by n/2^k, while total arithmetic energy improves by a smaller, bounded factor that we quantify with a cost model. We describe a scatter-accumulate processing element (SA-PE) that replaces the MAC unit in a weight-stationary systolic array, with a load/stream/reduce/drain schedule in which a small, time-shareable multiplier runs only 2^k times per tile. Because decoded weights are not stored, local weight memory shrinks by up to w_d/k for w_d-bit decoded weights. An RTL implementation synthesized for FPGA and compared with a matched MAC array shows that an unshared SA-PE is larger than a MAC PE, and that the saving appears when the reduction multiplier is shared across PEs. Software models confirm exact integer equivalence and floating-point error no worse than the conventional pipeline. We do not claim the underlying identity is new, and we discuss related work on weight sharing and lookup-based kernels.