FPGA-Based Neural Network Acceleration

The field studies how to map neural-network inference and training onto reconfigurable FPGA logic for edge and real-time systems with tight power or latency limits. Common approaches combine quantization and pruning with pipelined dataflow, systolic or time-multiplexed compute, and high-level synthesis tools such as FINN and hls4ml; LUT-native and event-driven designs target workloads suited to FPGA primitives. Work spans CNNs, transformers, graph networks, and spiking neural networks, using techniques such as sparse execution, on-chip memory reuse, and heterogeneous FPGA systems. The central challenge is balancing accuracy and predictable end-to-end latency against limited logic, compute, memory bandwidth, and energy, while ensuring results hold across devices and deployment conditions.