On-Device Training

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On-device training studies how models can learn from local data without relying on cloud retraining, supporting personalization, continual adaptation, and privacy-sensitive applications. Approaches range from full fine-tuning and parameter-efficient methods such as LoRA to prototype updates, local learning rules, and zeroth-order optimization that reduce memory or avoid backpropagation. Hardware and runtime work uses quantization, pruning, specialized accelerators, and memory-aware scheduling to fit training on phones, microcontrollers, FPGAs, and neuromorphic devices; evaluations span tasks such as keyword spotting, biosignal classification, and image recognition. A central tension is preserving accuracy while meeting tight memory, energy, and thermal limits, and many methods still need validation under sustained use and real-world distribution shifts.

Latest papers

38 papers13 papers in the last four weeks, against 2 the four weeks before. 0.1% of all new papers.

TsetlinWiSARD: On-Chip Training of Weightless Neural Networks using Tsetlin Automata on FPGAs
Mar 25, 2026Shengyu Duan, Marcos L. L. Sartori, Rishad Shafik +1On-Device Training FPGA-Based Neural Network Acceleration
Microsystems Research Group, Newcastle University · Literal Labs, Newcastle upon Tyne, UK
Mixed-signal implementation of feedback-control optimizer for single-layer Spiking Neural Networks
Mar 25, 2026Jonathan Haag, Christian Metzner, Dmitrii Zendrikov +4On-Device Training Neuromorphic Computing
Institute of Neuroinformatics, University of Zürich and ETH Zürich, Zürich, Switzerland · AI Center, ETH, Zürich, Switzerland · Digital Society Initiative, University of Zurich, Switzerland
DAPA: Distribution Aware Piecewise Activation Functions for On-Device Transformer Inference and Training
Mar 19, 2026Maoyang Xiang, Bo WangNeural Network Activation Functions Efficient Transformer Inference
Information Systems Technology and Design Singapore University of Technology and Design Singapore
TrainDeeploy: Hardware-Accelerated Parameter-Efficient Fine-Tuning of Small Transformer Models at the Extreme Edge
Mar 10, 2026Run Wang, Victor J. B. Jung, Philip Wiese +3On-Device Training Edge ML
Integrated Systems Laboratory (IIS), ETH Zurich, Switzerland · Department of Electrical, Electronic and Information Engineering (DEI), University of Bologna, Italy · Department of Control and Computer Engineering (DAUIN), Politecnico di Torino, Italy
Orion: Characterizing and Programming Apple's Neural Engine for LLM Training and Inference
Mar 6, 2026Ramchand KumaresanNeural Network Hardware Acceleration On-Device Training
OnDA: On-device Channel Pruning for Efficient Personalized Keyword Spotting
Feb 25, 2026Matteo Risso, Alessio Burrello, Daniele Jahier PagliariNeural Network Pruning Structured Pruning
Politecnico di Torino, Italy
Online Continual Learning on Intel Loihi 2 via a Co-designed Spiking Neural Network
Nov 3, 2025Elvin Hajizada, Danielle Rager, Timothy Shea +5Online Continual Learning Incremental Learning
Institute of Informatics, University of Munich (LMU), Munich, Germany · Intel Labs, Intel Corporation, Santa Clara, CA, USA · Southwest Research Institute, San Antonio, TX, USA +3
EmbodiTTA: Resource-Efficient Test-Time Adaptation for Embodied Visual Systems
May 2, 2025Xiao Ma, Young D. Kwon, Dong MaTest-Time Adaptation Continual Test-Time Adaptation
Singapore Management University, Singapore · Samsung AI Center–Cambridge, United Kingdom · University of Cambridge, United Kingdom

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TsetlinWiSARD: On-Chip Training of Weightless Neural Networks using Tsetlin Automata on FPGAs

Shengyu Duan, Marcos L. L. Sartori, Rishad Shafik, Alex Yakovlev

Microsystems Research Group, Newcastle University · Literal Labs, Newcastle upon Tyne, UK

On-Device Training FPGA-Based Neural Network Acceleration

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Increasing demands for adaptability, privacy, and security at the edge have persistently pushed the frontiers for a new generation of machine learning (ML) algorithms with training and inference capabilities on-chip. Weightless Neural Network (WNN) is such an algorithm that is principled on lookup table based simple neuron structures. As a result, it offers architectural benefits, such as low-latency, low-complexity inference, compared to deep neural networks that depend heavily on multiply-accumulate operations. However, traditional WNNs rely on memorization-based one-shot training, which either leads to overfitting and reduced accuracy or requires tedious post-training adjustments, limiting their effectiveness for efficient on chip training. In this work, we propose TsetlinWiSARD, a training approach for WNNs that leverages Tsetlin Automata (TAs) to enable probabilistic, feedback-driven learning. It overcomes the overfitting of WiSARD's one-shot training with iterative optimization, while maintaining simple, continuous binary feedback for efficient on-chip training. Central to our approach is a field programmable gate array (FPGA)-based training architecture that delivers state-of-the-art accuracy while significantly improving hardware efficiency. Our approach provides over 1000x faster training when compared with the traditional WiSARD implementation of WNNs. Further, we demonstrate 22% reduced resource usage, 93.3% lower latency, and 64.2% lower power consumption compared to FPGA-based training accelerators implementing other ML algorithms.