cs.ARApr 22, 2025
SaveFPGA-Based Neural Network Accelerators for Space Applications: A Survey
Abstract
Space missions are becoming increasingly ambitious, necessitating high-performance onboard spacecraft computing systems. In response, field-programmable gate arrays (FPGAs) have garnered significant interest due to their flexibility, cost-effectiveness, and radiation tolerance potential. Concurrently, neural networks (NNs) are being recognized for their capability to execute space mission tasks such as autonomous operations, sensor data analysis, and data compression. This survey serves as a valuable resource for researchers aiming to implement FPGA-based NN accelerators in space applications. By analyzing existing literature, identifying trends and gaps, and proposing future research directions, this work highlights the potential of these accelerators to enhance onboard computing systems.
Figures & tables
Figure 1. Abstract representation of an FPGA, showing logic blocks, programmable interconnect, and IOs Abstract representation of the structure of an FPGA, showing logic blocks, programmable interconnect, and IO pad. Abstract representation of the structure of an FPGA, showing logic blocks, programmable interconnect, and IO pad. The figure illustrates the internal architecture of an FPGA, highlighting its key components. These components include logic blocks, the basic building blocks of the FPGA; programmable interconnects that enable flexible connections between logic blocks; and input/output (I/O) pads that facilitate communication with external devices.
Figure 2. Architecture of an FPGA-based NN accelerator Architecture of an FPGA-based NN accelerator Two FPGA-based NN accelerator paradigms. (a) Time-multiplexed: a PE array is reused across layers; a shared on-chip buffer stores weights and activations, feeds the array, and receives intermediate results for the next layer. Activations flow left to right and weights top to bottom. (b) Dataflow: each layer is mapped to dedicated PEs and memory, forming a pipeline.
Figure 3. Different fault tolerance design techniques Taxonomy of fault-tolerance techniques A diagram grouping fault-tolerance techniques into fault mitigation, fault detection, and fault recovery. Mitigation includes radiation-hardened devices and static redundancy such as TMR. Detection includes dynamic redundancy, duplication with comparison, and BIST. Recovery includes repair, replacement, and FPGA configuration-memory scrubbing.
| Key. | Task Type | FPGA Family | Hardware Design |
| Zhuang and Low (2014) ( Zhuang and Low, 2014 ) | Segmentation | Spartan 3A | – |
| Chen et al. (2018) ( Chen et al., 2018b ) | Classification | – | HDL |
| Jain et al. (2018) ( Jain et al., 2018 ) | Classification | Spartan 6 | – |
| Hashimoto et al. (2018) ( Hashimoto et al., 2018 ) | Classification | Zynq 7000 SoC | FINN |
| Pitsis et al. (2019) ( Pitsis et al., 2019 ) | Classification | Zynq UltraScale+ MPSoC | – |
| Sabogal et al. (2019 ( Sabogal et al., 2019 ) , 2021 ( Sabogal et al., 2021 ) ) | Segmentation | Zynq 7000 SoC & Zynq UltraScale+ MPSoC | HLS |
Table 1. Distinctive characteristics of each earth observation and remote sensing system reviewed in this section
| Key. | Data Origin | Task Type | NN Architecture | FPGA Family | Hardware Design |
| Gankidi and Thangavelautham (2017) ( Gankidi and Thangavelautham, 2017 ) | In-Situ | Classification | MLP | Virtex 7 | – |
| Lent (2020) ( Lent, 2020 ) | In-Situ | Classification | SNN | Zynq 7000 SoC | HLS |
| Cosmas and Kenichi (2020) ( Cosmas and Kenichi, 2020 ) | Remote | Keypoint Detection | CNN | Zynq UltraScale+ MPSoC | AMD DPU |
| Jiang and Sha (2023) ( Jiang and Sha, 2023 ) | In-Situ | Classification | SNN | Virtex 7 | – |
| Ekblad et al. (2023) ( Ekblad et al., 2023 ) | Remote | Object Detection | CNN | Zynq UltraScale+ MPSoC | AMD DPU |
| Carmeli and Ben-Moshe (2023) ( Carmeli and Ben-Moshe, 2023 ) | Remote | Classification | SOM | Cyclone V | – |
Table 2. Distinctive characteristics of each spacecraft perception, autonomy, and navigation system reviewed in this section
| Key. | Data Origin | Task Type | NN Architecture | FPGA Family | Hardware Design |
| Kesuma et al. (2019) ( Kesuma et al., 2019 ) | In-Situ | Classification | MLP | Virtex-5QV | LEON3 |
| Ma et al. (2019) ( Ma et al., 2019 ) | Remote | Segmentation | Fully-Connected Autoencoder | Zynq UltraScale+ MPSoC | HLS |
| Perryman et al. (2023) ( Perryman et al., 2023 ) | – | Classification | CNN | Versal | HLS |
| Coca and Datcu (2023) ( Coca and Datcu, 2023 ) | Remote | Classification | CNN | Zynq UltraScale+ MPSoC | AMD DPU |
| Pacini et al. (2023) ( Pacini et al., 2023b ) | In-Situ | Classification | RNN | Kintex UltraScale | HDL |
| Benelli et al. (2024) ( Benelli et al., 2024 ) | – | Classification | CNN | Zynq UltraScale+ MPSoC | GPU@SAT |
Table 3. Distinctive characteristics of the anomaly-detection and undefined-use-case systems reviewed in this subsection
Figure 4. Task types found in the literature Neural Network types used in the surveyed literature Neural Network types used in the surveyed literature. The pie chart shows that most works employ classification networks, followed by segmentation and object detection networks. Other task types are less common, and transformers are not used in any of the works.
Figure 5. Distribution of hardware implementation methods by year in the surveyed literature Distribution of hardware implementation methods by year in the surveyed literature Stacked bar chart showing the distribution of hardware implementation methods across the surveyed literature from 2014 to 2024. The chart highlights that while HDLs (such as Verilog, SystemVerilog, and VHDL) dominate overall, higher-level frameworks and particularly AMD DPU implementations have grown in recent years.
Figure 6. Influence of operations and parameters on inference time and throughput Influence of operations and parameters on inference time and throughput Influence of operations and parameters on inference time and throughput. The first figure shows the number of operations vs. inference time, while the second figure shows the number of parameters vs. throughput. In the first figure, we see an increase in inference time with the number of operations, while in the second figure, we see a decrease in throughput with the number of parameters.
Figure 7. Influence of DSPs and BRAM on performance Influence of DSPs and BRAM on performance Influence of DSPs and BRAM on performance. The first figure shows the number of DSPs vs. performance (GOP/s), while the second figure shows the number of BRAM vs. performance (GOP/s). The first and second figures show an increase in performance with the number of DSPs and BRAMs, respectively.
Figure 8. Performance vs. power consumption Performance vs. power consumption Performance vs. power consumption. The figure shows the performance (GOP/s) vs. power consumption (W). We see a general proportionality between performance and power consumption, with some exceptions.
Figure 9. Influence of parameters and operations on per-inference energy consumption Influence of parameters and operations on per-inference energy consumption Influence of parameters and operations on per-inference energy consumption. The first figure shows the number of parameters vs. per-inference energy consumption, while the second figure shows the number of operations vs. per-inference energy consumption. The first figure shows an increase in per-inference energy consumption with the number of parameters. In contrast, the second figure shows an increase in per-inference energy consumption with the number of operations.
Appendix figures & tables1 asset
Supplementary material from the paper’s appendix.
Appendix
| Algorithm-related Metrics | Hardware-related Metrics |
| Application: Identifies the specific space-related task. | Board: Specifies the target development platform. |
| Task Type/s: Learning objective the model is designed to solve. | FPGA: Specifies the exact silicon chip utilized. |
| NN Architecture: The specific underlying neural network structure (e.g., CNN, SNN, MLP). | Hardware Implementation: Details the hardware description language or tool used. |
| Data Origin: Identifies the source of the data processed. | Accelerator Architecture (NN Flexibility): Characterizes the main hardware design paradigm (e.g., dataflow or time-multiplexed). (Defines if the accelerator can run different NN models, a specific model with variable parameters, or a specific model with specific parameters, without changing the FPGA design.) |
| Dataset/s: Details the actual data compilation used for training and benchmarking. | FPGA Resource Consumption: Quantifies the utilization of on-chip components, including LUTs, FFs, DSPs, and BRAMs. |
| Training Method: Specifies whether training is on-board or off-board, and if supervised or unsupervised. | Frequency (MHz): Tracks the operating clock speed of the synthesized hardware design. |
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