Flexi-NeurA: A Flexible Neuromorphic Accelerator with Adaptive Bit-Precision Exploration for Edge Devices
Authors: Mohammad Farahani, Mohammad Rasoul Roshanshah, Saeed Safari
Organizations: High-Performance Embedded Architecture Laboratory (HiPEAL), School of Electrical and Computer Engineering, College of Engineering, University of Tehran, Tehran, Iran
Neuromorphic accelerators promise unparalleled energy efficiency and computational density for spiking neural networks, especially in wearable biomedical devices and neural prosthetics where power constraints are stringent. However, most existing platforms exhibit rigid architectures with limited configurability, restricting their adaptability to heterogeneous biological signals and diverse design objectives. To address these limitations, we present Flexi-NeurA--a flexible neuromorphic accelerator that unifies configurability and efficiency. Flexi-NeurA allows users to customize neuron models, network structures, and precision settings at design time. By pairing these design-time configurability features with a time-multiplexed and event-driven processing approach, Flexi-NeurA reduces the required hardware resources and total power while preserving high efficiency and low inference latency. Complementing this, we introduce Flex-plorer, a design-space exploration tool that determines cost-effective fixed-point precisions for critical parameters--such as decay factors, synaptic weights, and membrane potentials--based on user-defined trade-offs between accuracy and resource usage. Based on the configuration selected through the Flex-plorer process, RTL code is configured to match the specified design. Comprehensive evaluations across distinct domains--biomedical auditory processing, dynamic vision sensor gesture recognition, and standard vision classification--demonstrate that the hardware/software co-framework successfully balances accuracy and power budgets for diverse applications. A 3-layer 256-128-10 fully connected network with LIF neurons mapped onto two processing cores achieves 96.23% accuracy on MNIST with 1.1 ms inference latency, utilizing only 1,623 logic cells, 7 BRAMs, and 111 mW of total power--demonstrating superior resource efficiency compared to SoTA hardware baselines.
Figure 2: Spiking neuron models: (A) IF, (B) LIF, and (C) Synaptic. To facilitate a clear comparison of their internal dynamics and output behaviors, the exact same input spike pattern is used across all three models.
Figure 3: Top-level architecture of the Flexi-NeurA processing core and its main functional units.
Figure 4: Multi-core system organization showing AER-based inter-layer communication and layer-to-core mapping.
Figure 5: Block diagram of the Configurable Neuron Unit (CNU), illustrating the datapath and interaction between the Controller, Synaptic/Neuron Memories, and the Neuron Core.
Figure 6: Coefficient Generator (CG) structure based on a shift-and-add network. The 9-bit DecayRate[8:0] configures selectable shifts to approximate any leakage factor in the [0,1] range with 1/256 resolution.
Figure 7: SPI communication timing. (A) Configuration and write operations using 23-bit address and data fields. (B) Read operation with 23-bit address input and 23-bit data output via MISO.
Figure 8: Configuration registers and their functional destinations within the Flexi-NeurA core.
Figure 9: Controller state machine for handling read/write operations across neuron, feedforward synapse, and recurrent synapse memories, including SPI wait synchronization.
Figure 10: State machine for the controller’s Spike Integration and Leakage & Spike Generation phases. Incoming spike packets from feedforward or recurrent paths trigger per-neuron updates, followed by potential evaluation, spike emission, and control signaling (EOTS/EOIN).
Figure 11: Overview of the Flex-plorer framework for design-space exploration and hardware generation.
Figure 12: End-to-end data flow and hardware mapping for the SHD auditory processing case study.
Figure 13: End-to-end data flow and hardware mapping for DVS-based gesture processing.
Dataset
Neuron
Network
Time Steps
Accuracy (%)
Energy (mJ)
SHD
IF
FF
70
61
1.48
IF
ATAF
70
63
1.85
IF
ATAT
70
65
2.77
LIF
FF
70
61
1.48
LIF
ATAF
70
63
1.85
LIF
ATAT
70
67
2.77
Table 1: Accuracy and Energy Trade-offs for SHD, DVS, and MNIST across different configurations.
Figure 14: Design-space exploration of quantization precision for (a) DVS and (b) MNIST benchmarks, illustrating the trade-off between hardware cost and accuracy cost. The selected candidate is the one that minimizes the total cost—calculated as the sum of the accuracy cost and hardware cost.
Design
Liu et al. [ 29 ]
Navarez et al. [ 34 ]
Li et al. [ 33 ]
Gerlinghoff et al. [ 32 ]
Panchapakesan et al. [ 27 ]
Khodamoradi et al. [ 30 ]
Year
2023
2021
2023
2022
2021
2021
fclk [MHz]
100
200
300
200
200
N/R
Neuron bw
8
8
12
N/R
4
N/R
Weights bw
8
8
8
3
4
N/R
Update
Clock
Clock
Clock
Clock
Event
Event
Model
IF
Spike-by-Spike (SbS)
LIF
LIF
IF
LIF
Table 2: Comparison of Flexi-NeurA with recent FPGA-based accelerators on the MNIST benchmark.
Sparse DNN accelerators specialize in ANN or SNN execution, leaving energy or latency on the table when workload characteristics vary within a layer. Hybrid accelerator designs that switch modes at layer or tile granularity suffer from low PE utilization since one core type idles whenever the other is active. NeuroFlex is the first accelerator to assign every output element independently to ANN or SNN execution mode with zero accuracy loss. We extend integer-exact ANN-SNN equivalence from layers to individual output elements, thereby enabling mode switching with no conversion error. An offline cost-guided scheduler scores each element by its marginal energy-delay trade-off and packs work across PEs, achieving 97-99% PE utilization compared to 40-45% for layer-wise hybrids. NeuroFlex reduces EDP by 57-67% over a strong ANN-only baseline and delivers up to 2.5x speedup over a dual-sparse SNN-only baseline. Our cost-guided scheduler improves throughput by 16-19% over random element assignment across vision, language, and transformer workloads.
Electrical Engineering Indian Institute of Technology Madras Chennai, India · Computer Science and Engineering Indian Institute of Technology Madras Chennai, India
Sparse DNN accelerators specialize in ANN or SNN execution, leaving energy or latency on the table when workload characteristics vary within a layer. Hybrid accelerator designs that switch modes at layer or tile granularity suffer from low PE utilization since one core type idles whenever the other is active. NeuroFlex is the first accelerator to assign every output element independently to ANN or SNN execution mode with zero accuracy loss. We extend integer-exact ANN-SNN equivalence from layers to individual output elements, thereby enabling mode switching with no conversion error. An offline cost-guided scheduler scores each element by its marginal energy-delay trade-off and packs work across PEs, achieving 97-99% PE utilization compared to 40-45% for layer-wise hybrids. NeuroFlex reduces EDP by 57-67% over a strong ANN-only baseline and delivers up to 2.5x speedup over a dual-sparse SNN-only baseline. Our cost-guided scheduler improves throughput by 16-19% over random element assignment across vision, language, and transformer workloads.
Electrical Engineering Indian Institute of Technology Madras Chennai, India · Computer Science and Engineering Indian Institute of Technology Madras Chennai, India
Spiking Neural Networks (SNNs) promise significant advantages over conventional Artificial Neural Networks (ANNs) for applications requiring real-time processing of temporally sparse data streams under strict power constraints -- a concept known as the Neuromorphic Advantage. However, the limited availability of neuromorphic hardware creates a substantial simulation-to-hardware gap that impedes algorithmic innovation, hardware-software co-design, and the development of mature open-source ecosystems. To address this challenge, we introduce Yet Another Neuromorphic Accelerator (YANA), an FPGA-based digital SNN accelerator designed to bridge this gap by providing an accessible hardware and software framework for neuromorphic computing. YANA implements a five-stage, event-driven processing pipeline that fully exploits temporal and spatial sparsity while supporting arbitrary SNN topologies through point-to-point neuron connections. The architecture features an input preprocessing scheme that maintains steady event processing at one event per cycle without buffer overflow risks, and implements hardware-efficient event-driven neuron updates using lookup tables for leak calculations. We demonstrate YANA's sparsity exploitation capabilities through experiments on the Spiking Heidelberg Digits dataset, showing near-linear scaling of inference time with both spatial and temporal sparsity levels. Deployed on the accessible AMD Kria KR260 platform, a single YANA core utilizes 740 LUTs, 918 registers, 7 BRAMS and 24 URAMs, supporting up to 217 synapses and 210 neurons. We release the YANA framework as an open-source project, providing an end-to-end solution for training, optimizing, and deploying SNNs that integrates with existing neuromorphic computing tools through the Neuromorphic Intermediate Representation (NIR).
Brian Pachideh, Sven Nitzsche, Moritz Neher +5
FZI Research Center for Information Technology, Karlsruhe, Germany · Karlsruhe Institute of Technology, Karlsruhe, Germany · Infineon Technologies, Dresden, Germany