cs.ARFeb 20, 2026

Flexi-NeurA: A Flexible Neuromorphic Accelerator with Adaptive Bit-Precision Exploration for Edge Devices

Authors: Mohammad Farahani, Mohammad Rasoul Roshanshah, Saeed Safari

Organizations: High-Performance Embedded Architecture Laboratory (HiPEAL), School of Electrical and Computer Engineering, College of Engineering, University of Tehran, Tehran, Iran

Abstract

Neuromorphic accelerators promise unparalleled energy efficiency and computational density for spiking neural networks, especially in wearable biomedical devices and neural prosthetics where power constraints are stringent. However, most existing platforms exhibit rigid architectures with limited configurability, restricting their adaptability to heterogeneous biological signals and diverse design objectives. To address these limitations, we present Flexi-NeurA--a flexible neuromorphic accelerator that unifies configurability and efficiency. Flexi-NeurA allows users to customize neuron models, network structures, and precision settings at design time. By pairing these design-time configurability features with a time-multiplexed and event-driven processing approach, Flexi-NeurA reduces the required hardware resources and total power while preserving high efficiency and low inference latency. Complementing this, we introduce Flex-plorer, a design-space exploration tool that determines cost-effective fixed-point precisions for critical parameters--such as decay factors, synaptic weights, and membrane potentials--based on user-defined trade-offs between accuracy and resource usage. Based on the configuration selected through the Flex-plorer process, RTL code is configured to match the specified design. Comprehensive evaluations across distinct domains--biomedical auditory processing, dynamic vision sensor gesture recognition, and standard vision classification--demonstrate that the hardware/software co-framework successfully balances accuracy and power budgets for diverse applications. A 3-layer 256-128-10 fully connected network with LIF neurons mapped onto two processing cores achieves 96.23% accuracy on MNIST with 1.1 ms inference latency, utilizing only 1,623 logic cells, 7 BRAMs, and 111 mW of total power--demonstrating superior resource efficiency compared to SoTA hardware baselines.

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