RTLocating: Intent-aware RTL Localization for Hardware Design Iteration

Changwen Xing; Yanfeng Lu; Lei Qi; Chenxu Niu; Jie Li; Xi Wang; Yong Chen; Jun Yang

cs.ETFeb 28, 2026

RTLocating: Intent-aware RTL Localization for Hardware Design Iteration

Authors: Changwen Xing, Yanfeng Lu, Lei Qi, Chenxu Niu, Jie Li, Xi Wang, Yong Chen, Jun Yang

Organizations: School of Integrated Circuits, Southeast University, Nanjing, China · National Center of Technology Innovation for EDA, Nanjing, China · School of Computer Science and Engineering, Southeast University, Nanjing, China · Department of Computer Science, Texas Tech University, Lubbock, USA

Abstract

Industrial chip development is inherently iterative, favoring localized, intent-driven updates over rewriting RTL from scratch. Yet most LLM-Aided Hardware Design (LAD) work focuses on one-shot synthesis, leaving this workflow underexplored. To bridge this gap, we for the first time formalize $Δ$ Spec-to-RTL localization, a multi-positive problem mapping natural language change requests ( $Δ$ Spec) to the affected Register Transfer Level (RTL) syntactic blocks. We propose RTLocating, an intent-aware RTL localization framework, featuring a dynamic router that adaptively fuses complementary views from a textual semantic encoder, a local structural encoder, and a global interaction and dependency encoder (GLIDE). To enable scalable supervision, we introduce EvoRTL-Bench, the first industrial-scale benchmark for intent-code alignment derived from OpenTitan's Git history, comprising 1,905 validated requests and 13,583 $Δ$ Spec-RTL block pairs. On EvoRTL-Bench, RTLocating achieves 0.568 MRR and 15.08% R@1, outperforming the strongest baseline by +22.9% and +67.0%, respectively, establishing a new state-of-the-art for intent-driven localization in evolving hardware designs.

Figures & tables

Figure 1: Intent-Driven RTL Change Localization vs. Surface Matching

Figure 2: Overview of RTLocating Framework.

Tier	LOC Range	#IPs	Share
Lightweight	$<1$ k	6	16.2%
Small/Utility	1k–5k	15	40.6%
Medium-Scale	5k–10k	8	21.6%
Large-Scale	10k–20k	6	16.2%
High-Complexity	$>20$ k	2	5.4%
Total	–	37	100.0%

Table 1: OpenTitan IP Complexity Statistics (LOC).

Model	Setting	MRR	MAP	Recall (%)			Hit (%)
Model	Setting	MRR	MAP	R@1	R@5	R@10	H@1	H@5	H@10
Lexical & General Dense Retrievers
BM25	-	0.421	0.292	8.33	28.02	33.90	28.18	59.09	65.45
all-MiniLM-L6-v2	Off-the-shelf	0.373	0.229	7.39	25.56	31.04	22.73	54.55	64.55
Code-Specific Pre-trained Models
CodeBERT	Off-the-shelf	0.110	0.046	0.86	2.21	4.98	5.45	15.45	21.82

Table 2: Main Retrieval Performance of RTLocating and Baselines.

Model	Params (M)	Latency (ms)
CodeBERT	124.65	7.23
GraphCodeBERT	124.65	7.14
UniXcoder	125.93	7.15
Sparse–Dense Hybrid	125.93	14.32
RTLocating (Ours)	23.04	6.25

Table 3: Comparison of Model Parameters and Inference Latency.

Figure 4: Intent-aware Routing Analysis: (a) encoder weight distributions; (b) PCA of weight clusters; (c) top TF-IDF keywords.

Figure 5: Robustness Analysis via Slope Chart.

Appendix figures & tables5 assets

Supplementary material from the paper’s appendix.

Appendix

Component	Hyperparameter	Value
General Settings
	Frameworks	PyTorch, PyG
	Random Seed	36
	Optimizer	AdamW
Text Expert
	Base Model	MiniLM-L6

Appendix

Table 4: Detailed hyperparameters and configurations.

Subsystem Category	IP Modules	Functional Description
Cryptography	aes , hmac , kmac ,	Symmetric encryption, hashing, key management,
& Security	keymgr , csrng	and hardware-based entropy sourcing.
Computing	otbn	High-complexity Big Number accelerator for public-key cryptography.
Infrastructure	tlul , prim	On-chip bus protocols (TileLink) and fundamental hardware primitives.
Storage &	flash_ctrl , otp_ctrl ,	Controller logic for non-volatile memory, SRAM,
Lifecycle	lc_ctrl , sram_ctrl	and hardware lifecycle state management.

Appendix

Table 5: Functional Diversity and Subsystem Representation

Criterion	Pass rate (%)
Label correctness	98.0
$S_{\text{old}}/S_{\text{new}}$ behavioral fidelity	95.0
Context grounded (no change narration)	96.0
Intention supported by message	99.0
Block localization consistent with diff/AST	97.0

Appendix

Table 6: Manual audit checklist and outcomes.

Statistic	Time (s)
#Snapshots	25
Min / Median / Mean	0 / 9 / 17.1
P90 / P95	33.2 / 54.8
Max	110
Total	428

Appendix

Table 7: Offline DTG construction time over 25 representative snapshots.

Metric	Min	Median	Mean	Max
Snapshots per IP	5	71	88.0	389
Avg Nodes per IP	38.2	278.8	418.5	1,980.1
Avg Edges per IP	231	18,607	173,633	1,682,282

Appendix

Table 8: Statistical summary of DTGs across OpenTitan IPs.

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HINT: Toward an Executable Hardware-Intent Representation Layer for LLM-Driven RTL Generation

Tairan Cheng, Yi Liu, Dongsheng Zuo, Zhengyuan Shi+5

The Chinese University of Hong Kong Hong Kong, China · Southeast University Nanjing, China

Electronic Design Automation LLM-Based Program Synthesis RTL Code Generation

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Generating implementation-quality RTL with large language models (LLMs) remains difficult because direct generation must resolve microarchitecture while simultaneously producing and debugging low-level code. We present HINT, an executable hardware-intent intermediate representation layer between behavioral specifications or executable oracles and RTL. HINT makes RTL-relevant microarchitecture explicit, supports pre-RTL checking, and supplies explicit RTL-lowering obligations. We evaluate HINT using both a minimal single-agent flow and a full staged workflow. Across seven operator cases, the HINT-mediated route, with no post-synthesis QoR refinement, produces contract-compliant synthesizable RTL on 7/7 cases; Direct C2RTL and C2HLSC apply to five cases and succeed on 5/5 and 1/5, respectively. Under matched Design Compiler synthesis, HINT reduces area by 5.0%--26.2% relative to five manual RTL implementations and by 8.9%--86.1% relative to five accepted Direct C2RTL results. RealBench AES and SDC, together with a Vortex VPU synthesizing to 561.67k~

μ\mathrm{m}^2

, further demonstrate specification-driven, protocol-rich, memory-rich, and hierarchical designs. In the controlled operator study, the HINT-mediated route shows better observed convergence and avoids the severe implementation-quality degradation seen in several direct-generation results.

Abstract

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