RTL Code Generation

Follow this topic Ask about this topic

RTL code generation studies how to turn natural-language requirements, diagrams, or executable references into hardware descriptions that behave correctly and meet physical design goals. Common approaches include prompting or fine-tuning large language models, decomposing designs into reusable modules, and using agents, retrieval, or intermediate representations to guide generation. Simulation, formal verification, synthesis, and timing analysis provide feedback, with benchmarks such as VerilogEval and RTLLM measuring correctness and hardware quality. A central tension is that passing tests does not guarantee good area, delay, or power, while benchmark results can also depend strongly on model settings and may not reflect complex, evolving specifications.

Latest papers

31 papers3 papers in the last four weeks, with none the four weeks before. 0.0% of all new papers.

Learn the Interface, Not the Implementation: Output Representation Dominates Training Regime in LLM-Based RTL Generation
Oct 19, 2026Siddharth Patel, Vikram Singh, Siddharth Savyasachi Malu +1RTL Code Generation Code Generation
Dept. of Electronics Engineering, Shiv Nadar Institution of Eminence, Delhi-NCR, India · STMicroelectronics, Greater Noida, India · AI Center of Excellence, Shiv Nadar Institution of Eminence, Delhi-NCR, India
CorrectRTL: Boost RTL Generation Quality Through Automated Self-Correction with Instruction Decomposition
Oct 18, 2026Jing Wang, Shang Liu, Hangan Zhou +4RTL Code Generation LLM Self-Correction
Hong Kong University of Science and Technology Clear Water Bay, Hong Kong
Pareto-Optimal RTL Code Generation via Multi-Objective Reinforcement Learning with Large Language Models
Oct 16, 2026Koki Takeshita, Kenji Uebayashi, Hikaru Tomonari +6RTL Code Generation Electronic Design Automation
Research & Development Group, Hitachi, Ltd.
HINT: Toward an Executable Hardware-Intent Representation Layer for LLM-Driven RTL Generation
Aug 7, 2026Tairan Cheng, Yi Liu, Dongsheng Zuo +6Electronic Design Automation LLM-Based Program Synthesis
The Chinese University of Hong Kong Hong Kong, China · Southeast University Nanjing, China
LACE: Large Language Model Aided Multi-Agent Framework for Agile RISC-V Instruction Extension
Aug 3, 2026Pingqing Zheng, Jiayin Qin, Fuqi Zhang +5LLM-Based Program Synthesis RTL Code Generation
University of Minnesota, Twin Cities, Minneapolis, Minnesota, USA · Columbia University, New York City, New York, USA · Northwestern University, Evanston, Illinois, USA
VeriTrace: Human-Like Temporal Exploration Completes Agentic Action Space
Aug 3, 2026Yu-Tung Liu, Cunxi YuLLM Agent Verification RTL Code Generation
University of Maryland, College Park College Park, USA
RTLCurator: Label-Efficient Data Curation for RTL Generation
Jul 31, 2026Siyang Cai, Cangyuan Li, Wenjing Chang +4Training Data Curation Training Data Selection
School of Advanced Interdisciplinary Sciences, University of Chinese Academy of Sciences, Beijing, China · CICS, Institute of Computing Technology, Chinese Academy of Sciences, Beijing, China · Computer Network Information Center, Chinese Academy of Sciences, Beijing, China +1
Interpretable and Verifiable Hardware Generation with LLM-Driven Stepwise Refinement
Jun 16, 2026You Li, Samuel Mandell, David Z. PanCode Generation LLM-Based Program Synthesis
The University of Texas at Austin · USA
LLM4RTL: Tool-Assisted LLM for RTL Generation
Jun 13, 2026Jing Jin, Robert Chu, Ning Yan +1Code Generation RTL Code Generation
UC Riverside · Riverside, CA, USA · Futurewei +1
OpenRTLSet: A Fully Open-Source Dataset for Large Language Model-based Verilog Module Design
Jun 9, 2026Jinghua Wang, Lily Jiaxin Wan, Sanjana Pingali +6LLM Fine-Tuning Electronic Design Automation
University of Illinois Urbana-Champaign
RTL-BenchLS: A Large-Scale Benchmark for RTL Reasoning and Generation with Large Language Models
Jun 8, 2026Jing Wang, Shang Liu, Wenji Fang +3LLM Evaluation Benchmark Design
Hong Kong University of Science and Technology
CASS-RTL: Correctness-Aware Subspace Steering for RTL Generation with LLMs
Jun 4, 2026Mohammad Akyash, Nowfel Mashnoor, Kimia Azar +1Code Generation LLM-Based Program Synthesis
Department of Electrical and Computer Engineering (ECE), University of Central Florida, Orlando, FL 32816, USA
Alpha-RTL: Test-Time Training for RTL Hardware Optimization
Jun 3, 2026Peilong Zhou, Zhirong Chen, Cangyuan Li +4RL for Language Models Test-Time Optimization
1SKLP, Institute of Computing Technology, Chinese Academy of Sciences · University of the Chinese Academy of Sciences · School of Advanced Interdisciplinary Sciences
StepPRM-RTL: Stepwise Process-Reward Guided LLM Fine-Tuning for Enhanced RTL Synthesis
Jun 2, 2026Prashanth Vijayaraghavan, Apoorva Nitsure, Luyao Shi +2RL for Code Generation Process Reward Models
IBM Research San Jose, CA, USA
EstRTL: Functional Estimation Guided RTL Code Generation
Jun 1, 2026Qi Xiong, Renzhi Chen, Bowei Wang +3Code Generation Agentic Code Generation
College of Computer Science and Technology, National University of Defense Technology, Changsha, China · Defense Innovation Institute, Academy of Military Science (AMS), Beijing, China · School of Computer Science and Technology, Shandong University, Qingdao, China +2
Verilog-Evolve: Feedback-Driven and Skill-Evolving Verilog Generation
May 26, 2026Zehua Pei, Hui-Ling Zhen, Yu Zhang +3Large Language Model-Guided Optimization Execution-Guided Code Generation
The Chinese University of Hong Kong · Huawei Technologies Co., Ltd
RTL-BenchMT: Dynamic Maintenance of RTL Generation Benchmark Through Agent-Assisted Analysis and Revision
May 15, 2026Jing Wang, Shang Liu, Hangan Zhou +1LLM Evaluation Electronic Design Automation
Hong Kong University of Science and Technology · Clear Water Bay, Hong Kong
ChipMATE: Multi-Agent Training via Reinforcement Learning for Enhanced RTL Generation
May 13, 2026Zhongkai Yu, Yichen Lin, Chenyang Zhou +12RL for Code Generation Code Generation
UCSD · Columbia University
From Mirage to Grounding: Towards Reliable Multimodal Circuit-to-Verilog Code Generation
Apr 30, 2026Guang Yang, Xing Hu, Xiang Chen +1Multimodal Grounding Code Generation
State Key Laboratory of Blockchain and Data Security, Zhejiang University, Hangzhou, China · Hangzhou High-Tech Zone (Binjiang) Institute of Blockchain and Data Security, Hangzhou, China · School of Artificial Intelligence and Computer Science, Nantong University, Nantong, China
How LLMs Fail and Generalize in RTL Coding for Hardware Design?
Apr 26, 2026Guan-Ting Liu, Chao-Han Huck Yang, Chenhui Deng +3LLM Evaluation Code Generation
NVIDIA Research
LEGO: An LLM Skill-Based Front-End Design Generation Platform
Apr 25, 2026Jincheng Lou, Ruohan Xu, Jiecheng Ma +3Electronic Design Automation Code Generation
School of IC, Peking University · School of EECS, Peking University · School of Microelectronics, Xidian University +2
ChipCraftBrain: Validation-First RTL Generation via Multi-Agent Orchestration
Apr 21, 2026Cagri EryilmazElectronic Design Automation Code Generation
ChipCraftX San Francisco, CA
Configuration Over Selection: Hyperparameter Sensitivity Exceeds Model Differences in Open-Source LLMs for RTL Generation
Apr 18, 2026Minghao Shao, Zeng Wang, Weimin Fu +5LLM Evaluation Language Model Generation Evaluation
NYU Tandon School of Engineering, USA · Kansas State University, USA · NYU Abu Dhabi, UAE
COEVO: Co-Evolutionary Framework for Joint Functional Correctness and PPA Optimization in LLM-Based RTL Generation
Apr 16, 2026Heng Ping, Peiyu Zhang, Shixuan Li +5Multi-Objective Evolutionary Optimization Code Generation
University of Southern California United States
Arch: An AI-Native Hardware Description Language for Register-Transfer Clocked Hardware Design
Apr 7, 2026Shuqing ZhaoElectronic Design Automation RTL Code Generation
RTLSeek: Boosting the LLM-Based RTL Generation with Multi-Stage Diversity-Oriented Reinforcement Learning
Mar 29, 2026Xinyu Zhang, Zhiteng Chao, Yonghao Wang +6RTL Code Generation LLM Post-Training
State Key Lab of Processors, Institute of Computing Technology, Chinese Academy of Sciences, China · University of Chinese Academy of Sciences, China · Peking University, China +1
IncreRTL: Traceability-Guided Incremental RTL Generation under Requirement Evolution
Mar 26, 2026Luanrong Chen, Renzhi Chen, Xinyu Li +3RTL Code Generation Code Generation
National University of Defense Technology, Changsha, China · Defense Innovation Institute, Academy of Military Sciences, Beijing, China · Qiyuan Lab, Beijing, China
VeriAgent: A Tool-Integrated Multi-Agent System with Evolving Memory for PPA-Aware RTL Code Generation
Mar 18, 2026Yaoxiang Wang, Qi Shi, ShangZhan Li +6RTL Code Generation Electronic Design Automation
Xiamen University · Tsinghua University · Harbin Institute of Technology
CODMAS: A Dialectic Multi-Agent Collaborative Framework for Structured RTL Optimization
Mar 17, 2026Che-Ming Chang, Prashanth Vijayaraghavan, Ashutosh Jadhav +4Electronic Design Automation RTL Code Generation
National Taiwan University · IBM Research
VeriGRAG: Enhancing LLM-Based Verilog Code Generation with Structure-Aware Soft Prompts
Sep 27, 2025Jiayu Zhao, Zehua Pei, Zetao Guo +2RTL Code Generation LLM Code Generation
University of Science and Technology of China

Oct 19, 2026J/K move · Enter open · S save

Learn the Interface, Not the Implementation: Output Representation Dominates Training Regime in LLM-Based RTL Generation

Siddharth Patel, Vikram Singh, Siddharth Savyasachi Malu, Rohit Singh

Dept. of Electronics Engineering, Shiv Nadar Institution of Eminence, Delhi-NCR, India · STMicroelectronics, Greater Noida, India · AI Center of Excellence, Shiv Nadar Institution of Eminence, Delhi-NCR, India

RTL Code Generation Code Generation

Open paper AskPDF arXiv

Large-language-model register-transfer-level (RTL) generation has concentrated on how to train the model: fine-tuning, continued pre-training, and reinforcement learning from a verifier. We argue this is the second-order question. On a bounded, formally specifiable task of generating single-error-correcting, double-error-detecting (SECDED) ECC memory wrappers, we hold the task, data, and correctness oracle fixed and vary two axes independently: the training regime (seven settings) and the output representation (four levels, from fully expanded flat Verilog to an eight-field configuration expanded by a deterministic generator). Because a reference generator exists, correctness is decided by formal equivalence over a design space of approximately ten million points, rather than sampled from a hand-written testbench. Two results follow. First, representation dominates: every representation close to raw RTL reaches a pass rate of at most 0.17, while the configuration reaches 0.83 with no training at all. Once the model emits the configuration, every training regime achieves a pass rate between 0.89 and 1.00. Second, raw RTL hits a hard output-length limit: a 512-bit design requires 44,237 tokens of flat Verilog compared with just 69 tokens for the configuration. Consequently, raw generation becomes infeasible above 32-bit data words rather than merely inaccurate. A model trained from scratch with fewer than 50 million parameters, combined with the verified generator, achieves 0.89 formal equivalence, compared with 1.00 for a 32-billion-parameter fine-tuned model, while using approximately 1600 times less inference energy per correct design. Inference energy also dominates amortized training energy. The lesson is to learn the interface, not the implementation.