cs.ARMar 14, 2026

Evaluating Four FPGA-accelerated Space Use Cases based on Neural Network Algorithms for On-board Inference

Authors: Pedro Antunes, Muhammad Ihsan Al Hafiz, Jonah Ekelund, Ekaterina Dineva, George Miloshevich, Panagiotis Gonidakis, Artur Podobas

Organizations: Department of Computer Science, Kungliga Tekniska högskolan (KTH), Stockholm, Sweden · Plasma-astrophysics, KU Leuven, Leuven, Belgium

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Abstract

Space missions increasingly deploy high-fidelity sensors that produce data volumes exceeding onboard buffering and downlink capacity. This work evaluates FPGA acceleration of neural networks (NNs) across four space use cases on the AMD ZCU104 board. We use Vitis AI (AMD DPU) and Vitis HLS to implement inference, quantify throughput and energy, and expose toolchain and architectural constraints relevant to deployment. Vitis AI achieves up to 34.16×\times higher inference rate than the embedded ARM CPU baseline, while custom HLS designs reach up to 5.4×\times speedup and add support for operators (e.g., sigmoids, 3D layers) absent in the DPU. For these implementations, measured MPSoC inference power spans 1.5-6.75 W, reducing energy per inference versus CPU execution in all use cases. These results show that NN FPGA acceleration can enable onboard filtering, compression, and event detection, easing downlink pressure in future missions.

Figures & tables

Fig. 1 : Example input to the VAE model: a cropped image of a solar active region showing the radial component of the Sun’s magnetic field. White areas indicate outward (positive) magnetic flux, and black areas indicate inward (negative) flux. The bright region near the center corresponds to a sunspot with strong positive polarity, surrounded by weaker areas of opposite polarity.
 # Parameters# Operations
VAE Encoder395,69283,417,100
CNetPlusScalar3,061,966918,241,400
multi-ESPERTA2460
LogisticNet8,19630,720
ReducedNet44,624502,961
BaselineNet915,492110,541,696
TABLE I : Summary of parameters and operations.
Fig. 2 : VAE encoder architecture (sampling and exponent handled on CPU).
Fig. 3 : CNetPlusScalar architecture after replacing leaky ReLU with ReLU.
Fig. 4 : Parallel multi-ESPERTA architecture (six shared-input models).
Fig. 7 : LogisticNet architecture.
Fig. 8 : Block diagram of our neural network accelerators integrated with Zynq MPSoC.
 LUTsFFsDSPsBRAMsURAMsClock/s Frequency
Available Resources230,000461,0001,72831296-
B4096 DPU (Vitis AI)102,154 (44%)199,192 (43%)1,420 (82%)165 (52%)92 (95%)75/100/300/600 MHz
ESPERTA HLS8,096 (4%)12,052 (3%)36 (2%)1.5 (1%)-100 MHz
LogisticNet HLS5,382 (2%)6,476 (1%)5 (0.29%)13 (4%)-100 MHz
ReducedNet HLS5,395 (2%)7,190 (2%)16 (1%)68.5 (22%)-100 MHz
BaselineNet HLS6,500 (3%)8,243 (2%)19 (1%)150.5 (48%)-100 MHz
TABLE II : Resource Utilization and Clock Frequency of Implementations on the ZCU104 FPGA
 Speed upFPSThroughputP BoardP MPSoCEnergy per Inference
VAE Encoder - CPU1 ×\times25.212.103 MOP/s12.125 W2.75 W109.08 mJ
VAE Encoder - Vitis AI24.06 ×\times606.6550,604 MOP/s15.337 W5.75 W9.48 mJ
CNetPlusScalar - CPU1 ×\times4.794,398 MOP/s12.862 W2.75 W574.11 mJ
CNetPlusScalar - Vitis AI34.16 ×\times163.51150,142 MOP/s15.987 W6.75 W41.28 mJ
ESPERTA - CPU1 ×\times6,9320.415 MOP/s11.725 W2.0 W0.29 mJ
ESPERTA - HLS5.33 ×\times37,2312 MOP/s10.6 W1.5 W0.04 mJ
TABLE III : Performance metrics for each application implemented on the ZCU104 board
Fig. 9 : ZCU104 (MPSoC) power consumption during inference of the VAE Encoder (1000 inputs).
Fig. 10 : ZCU104 (MPSoC) power consumption during inference of the CNetPlusScalar network (1000 inputs).
Fig. 11 : ZCU104 (MPSoC) power consumption during inference of the multi-ESPERTA network (1000000 inputs).
Fig. 12 : ZCU104 (MPSoC) power consumption during inference of MMS Neural Networks (LogisticNet, ReducedNet, BaselineNet). BaselineNet used 10 inputs due to higher computational complexity (others used 1000).
Fig. 13 : Detailed Power Consumption of the BaselineNet on the ZCU104 board
NetworkBoard# Param.FPSPower
VAE EncoderZCU104395,6926065.75 W
CNetPlusScalarZCU1043,061,9661636.75 W
LD-UNet [ 13 ]ZCU1045,65263214.1 W
CAE [ 11 ]ZCU1042,950,0002505.3 W
ResNet-50 [ 28 ]ZCU102-51-8530 W
mod. YOLOv4 [ 27 ]KV260-3.8-
TABLE IV : Comparison of Vitis AI performance with related work
NetworkBoard# Param.FPSPower
multi-ESPERTAZCU1042437,2311.5 W
LogisticNetZCU1048,1966461.75 W
CNN [ 12 ]ZCU104245,0003,6769.493 W
TCN+U-Net [ 29 ]Z-7020 1 1 1 Only the Zynq-7020 device was reported in the source; the specific development board was not specified.2,0000.980.196 W
TABLE V : Comparison of HLS performance with related work
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