Deep Reinforcement Learning-driven Edge Offloading for Latency-constrained XR pipelines

Sourya Saha; Saptarshi Debroy

cs.CVMar 17, 2026

Deep Reinforcement Learning-driven Edge Offloading for Latency-constrained XR pipelines

Authors: Sourya Saha, Saptarshi Debroy

Organizations: City University of New York

Abstract

Immersive extended reality (XR) applications introduce latency-critical workloads that must satisfy stringent real-time responsiveness while operating on energy- and battery-constrained devices, making execution placement between end devices and nearby edge servers a fundamental systems challenge. Existing approaches to adaptive execution and computation offloading typically optimize average performance metrics and do not fully capture the sustained interaction between real-time latency requirements and device battery lifetime in closed-loop XR workloads. In this paper, we present a battery-aware execution management framework for edge-assisted XR systems that jointly considers execution placement, workload quality, latency requirements, and battery dynamics. We design an online decision mechanism based on a lightweight deep reinforcement learning policy that continuously adapts execution decisions under dynamic network conditions while maintaining high motion-to-photon latency compliance. Experimental results show that the proposed approach extends the projected device battery lifetime by up to 163% compared to latency-optimal local execution while maintaining over 90% motion-to-photon latency compliance under stable network conditions. Such compliance does not fall below 80% even under significantly limited network bandwidth availability, thereby demonstrating the effectiveness of explicitly managing latency-energy trade-offs in immersive XR systems.

Figures & tables

Fig. 1 : The non-trivial conflict between Local vs Remote Offloading of XR workloads.

Fig. 2 : Overview of the edge-assisted interactive XR system model

Fig. 3 : Reinforcement learning control architecture where the DQN agent continuously observes battery, network, and latency conditions to select optimal quality, IMU rate, and processing mode configurations that extend device lifetime under real-time constraints.

Category	Value
Control and Timing
Decision interval	1 s
Target frame duration	50 ms (20 Hz)
MTP latency threshold	30 ms
Battery Model
Simulated battery capacity	16.6 Wh

TABLE I : Experimental configuration parameters

Panel of Figure 5 — Fig. 4 : Energy characteristics of LOCAL, OFFLOAD, and RL-Adaptive execution strategies under stable network condition.

Panel of Figure 6 — Fig. 5 : Performance characteristics of different execution strategies under stable network conditions, showing the trade-offs between energy efficiency and MTP latency behavior.

Panel of Figure 7 — Fig. 6 : Power consumption and efficiency in terms of MTP compliance per watt during normal network condition.

Panel of Figure 8 — Fig. 7 : RL behavior under network variability: bandwidth trace (a), resulting MTP latency over time (b), and execution mode switching (c).

Panel of Figure 9 — Fig. 8 : Energy characteristics of LOCAL, OFFLOAD, and RL-Adaptive execution strategies under variable network condition.

Panel of Figure 10 — Fig. 9 : MTP compliance of execution strategies under varying network conditions. The figure compares OFFLOAD and RL-Adaptive performance across bandwidth levels and shows overall strategy performance (LOCAL, OFFLOAD, RL-Adaptive) under stable and variable network scenarios.

Panel of Figure 11 — Fig. 10 : Learned policies for different network conditions.

Panel of Figure 12 — Fig. 11 : Comparison of battery depletion and average power consumption among RL-Adaptive and other adaptive approaches over stable and variable network conditions.

Panel of Figure 13 — Fig. 12 : Comparison of policies used for GREEDY (top) and THRESHOLD (bottom) over stable (left) and variable (right) network conditions.

Panel of Figure 14 — Fig. 13 : Hyperparameter sensitivity of the DQN policy under variable bandwidth conditions. (a) Effect of $\gamma$ , (b) Percentage Local Processing under different $\gamma$ , (c) Effect of epsilon decay rate, (d) Percentage Local Processing under different epsilon, (e) Effect of MTP penalty weight, (f) Percentage Local Processing under different MTP penalty weights.

Decision Interval	MTP Compliance	Avg Power (W)	LOCAL (%)
1.0 s (baseline)	83.8%	13.7	70.0
0.75 s	87.8%	15.5	72.9
0.5 s	84.0%	15.3	66.2

TABLE II : Hyperparameter Sensitivity Analysis under variable network conditions

Action	IMU Rate	Quality	Mode
0	HIGH	LOW	LOCAL
1	HIGH	LOW	OFFLOAD
2	HIGH	MEDIUM	LOCAL
3	HIGH	MEDIUM	OFFLOAD
4	HIGH	HIGH	LOCAL
5	HIGH	HIGH	OFFLOAD

TABLE III : Action Space Encoding

Metric	Value
LOCAL baseline	20.7 $\pm$ 0.1 W
LOCAL + plugins	22.4 $\pm$ 0.1 W
LOCAL + plugins + RL-Adaptive	23.3 $\pm$ 0.1 W
RL controller overhead	0.9 W (4.0%)
Decision latency
Median inference latency	157 $\mu$ s

TABLE IV : Measured overhead and architecture of the RL-Adaptive controller

Computation Offloading

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Jul 4, 2026J/K move · Enter open · S save

BitFair: A 12nm Bit-Serial CNN Accelerator with Learnable Early Termination and Adaptive Bit Ordering for Ultra-Low-Power XR Vision

Ang Li, Chang Gao

Department of Microelectronics, Delft University of Technology, Delft, The Netherlands

Efficient Neural Network Inference AI Accelerator Inference Energy-Efficient ML

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Extended Reality (XR) wearables require always-on perception within tight power envelopes of a few watts and motion-to-photon latency budgets below 20 ms, leaving only a few milliseconds for neural-network inference. Bit-serial computing is attractive for such energy-efficient neural network acceleration, but many existing architectures still process all bits even when ReLU sets the final output to zero. This paper presents BitFair, a software-hardware co-designed bit-serial CNN accelerator with learnable bit-level early termination and adaptive bit ordering, working under the ultra-low-power and strict latency requirements of XR applications. BitFair exploits dynamic bit-level sparsity by learning per-layer thresholds that trigger early termination when partial sums reliably predict that the final ReLU output will be zero. Furthermore, it searches for layer-wise bit orders that prioritize informative bits, maximizing early termination without sacrificing accuracy. A GlobalFoundries 12nm FinFET implementation with a core area of 0.34 mm^2, 104 KB on-chip memory, and voltage scaling from 0.55 to 0.70 V achieves sub-millisecond latency, up to 117.0 BTOPS/W, and 0.07 pJ/SOP. On IBM DVS128 Gesture and N-MNIST, BitFair achieves 96.5% and 97.7% accuracy, respectively, while improving effective energy efficiency by 4.0-22.1x and accuracy by up to 9.2% over prior fabricated XR vision accelerators.

Abstract

Computation Offloading

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