TRINE: A Token-Aware, Runtime-Adaptive FPGA Inference Engine for Multimodal AI
Organizations: University of California, Irvine · Purdue University Northwest · Qualcomm · Samsung
Abstract
Multimodal stacks that mix ViTs, CNNs, GNNs, and transformer NLP strain embedded platforms because their compute/memory patterns diverge and hard real-time targets leave little slack. TRINE is a single-bitstream FPGA accelerator and compiler that executes end-to-end multimodal inference without reconfiguration. Layers are unified as DDMM/SDDMM/SpMM and mapped to a mode-switchable engine that toggles at runtime among weight/output-stationary systolic, 1xCS SIMD, and a routable adder tree (RADT) on a shared PE array. A width-matched, two-stage top-k unit enables in-stream token pruning, while dependency-aware layer offloading (DALO) overlaps independent kernels across reconfigurable processing units to sustain utilization. Evaluated on Alveo U50 and ZCU104, TRINE reduces latency by up to 22.57x vs. RTX 4090 and 6.86x vs. Jetson Orin Nano at 20-21 W; token pruning alone yields up to 7.8x on ViT-heavy pipelines, and DALO contributes up to 79% throughput improvement. With int8 quantization, accuracy drops remain <2.5% across representative tasks, delivering state-of-the-art latency and energy efficiency for unified vision, language, and graph workloads-in one bitstream.
Figures & tables
| Work | AI | Sparse | Token |
| Workload | Kernel | Pruning | |
| This work | ViT+GNN+CNN+NLP | Yes | Run-time |
| ( Zhang et al., 2024b ) | CNN+GNN or ViT | Yes | No |
| ( Zhang et al., 2024a ) | CNN+GNN | No | No |
| ( Dong et al., 2023 ) | ViT | No | Run-time ∗ |
| ( You et al., 2023 ) | ViT | No | Compile-time ∗ |
| Alveo U50 | ZCU104 | |
| RPU Grid | 2×2 | 1×1 |
| MSE PE | 32×32 | 32×32 |
| Top- Eng. | Bitonic, Max- =256 | Dual-Layer, Max- =256 |
| Clock Freq. | 300 MHz | 200 MHz |
| LUT | 693,092 / 871,680 (79.51%) | 163,112 / 230,400 (70.80%) |
| FFs | 379,608 / 1,743,360 (21.77%) | 84,064 / 460,800 (18.24%) |
| Model | Label | Workload1 | Workload2 | Param. Count (M) |
| TinyCLIP (ViT + NLP) | A | ViT-8M/16 | TEXT-3M | 11 |
| B | ViT-39M/16 | TEXT-19M | 58 | |
| C | ViT-40M/32 | TEXT-19M | 59 | |
| D | ViT-61M/32 | TEXT-29M | 90 | |
| MDETR (CNN + NLP) | E | ResNet-18 | RoBERTa | 152 |
| F | ResNet-50 | RoBERTa | 166 |
| Unit | AMD DPU ’22 ( Inc., 2021 ) | VisionAgile TPDS’24 ( Zhang et al., 2024b ) | GCV-Turbo FCCM’24 ( Zhang et al., 2024a ) | HPTA FPL’23 ( Han and Liu, 2023 ) | FTRANS ISLPED’20 ( Li et al., 2020 ) | HeatViT HPCA’23 ( Dong et al., 2023 ) | SWAT ASP-DAC’24 ( Dong et al., 2024 ) | TRINE This Work | ||
| ML Workload | - | CNN, Transformer | CNN, ViT, GNN | CNN, GNN | Transformer | Transformer | ViT * | Swin | CNN, GNN, ViT, NLP | |
| Scheduling Mechanism | - | Sequential | Sequential | Sequential | Sequential | Sequential | Sequential | Sequential | Inter-Model Parallel | |
| Number Data Type | - | fixed-point8 | - | float16 | int8 | fixed-point16 | fixed-point8 | int8 | int8 | |
| FPGA Platform | - | ZCU 104 | Alveo U250 | Alveo U250 | ZCU 102 | VCU118 | ZCU102 | Alveo U50 | Alveo U50 | |
| Memory Bandwidth | GB/s | 19.2 | 77 | 77 | 19.2 | - | 19.2 | 316 | 316 | |
| Operating Frequency | MHz | 600/300 ** | 600/300 ** | 600/300 ** | 200 | - | 150 | 200 | 300 | |
| Workload | TinyCLIP | MDETR | MissionGNN | Workload | TinyCLIP | ||||
| Cfg. | A | B | F | G | J | L | Cfg. | A | B |
| Alveo U50 ∗ | 1.6 | 6.5 | 18.7 | 23.0 | 56.9 | 7.4 | ZCU104 ∗ | 4.4 | 20.8 |
| RTX 4090 ∗ | 37.1 | 49.9 | 21.7 | 28.4 | 50.1 | 44.1 | Jetson Orin Nano ∗ | 30 | 40.6 |
| Speedup (×) | 22.57 | 7.64 | 1.16 | 1.24 | 0.88 | 5.98 | Speedup (×) | 6.86 | 1.96 |
| Labels refer to Table 3 . ∗ Numbers are latencies (ms). | |||||||||
Efficient Multimodal Inference
Efficient multimodal inference reduces the compute, memory, latency, and energy needed to process image, video, audio, text, and sensor inputs.
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