ARCS: Autoregressive Circuit Synthesis with Topology-Aware Graph Attention and Spec Conditioning

Tushar Dhananjay Pathak

cs.LGMar 30, 2026

ARCS: Autoregressive Circuit Synthesis with Topology-Aware Graph Attention and Spec Conditioning

Authors: Tushar Dhananjay Pathak

Organizations: New York University

Abstract

This paper presents ARCS (Autoregressive Circuit Synthesis), a system for amortized analog circuit generation. ARCS produces complete, SPICE-simulatable designs (topology and component values) in milliseconds rather than the minutes required by search-based methods. A hybrid pipeline combines two learned generators, a graph VAE and a flow-matching model, with SPICE-based ranking. It achieves 99.9% simulation validity (reward 6.43/8.0) across 32 topologies using only 8 SPICE evaluations, 40x fewer than genetic algorithms. For single-model inference, a topology-aware Graph Transformer with Best-of-3 candidate selection reaches 85% simulation validity in 97ms, over 600x faster than random search. The key technical contribution adapts Group Relative Policy Optimization (GRPO) to multi-topology circuit reinforcement learning. GRPO resolves a critical failure mode of REINFORCE, cross-topology reward distribution mismatch, through per-topology advantage normalization. This improves simulation validity by +9.6 percentage points over REINFORCE in only 500 RL steps (10x fewer). Grammar-constrained decoding additionally guarantees 100% structural validity by construction via topology-aware token masking.

Figures & tables

Panel of Figure 1 — Fig. 1 : ARCS system overview. Top : Training pipeline. SPICE templates generate data, supervised pre-training learns the sequence distribution, and GRPO with SPICE-in-the-loop per-topology advantages refines value quality. Bottom : Inference pipeline. A target specification is tokenized, the trained model autoregressively generates component tokens with grammar-constrained masking, producing a valid circuit in $\sim$ 20 ms.

	Values	Specs	Graph	Valid	Speed	Data
AnalogGenie	×	×	×	93.2%	$\sim$ 1 s	Manual
LaMAGIC	×	×	✓	N/A	N/A	Synthetic
CircuitSynth	✓	×	×	N/A	$\sim$ 10 s	RL only
AstRL	✓	✓	×	N/A	N/A	RL only
DiffCkt	✓	×	✓	N/A	N/A	Synthetic
ARCS	✓	✓	✓	100% †	0.02 s	Auto

TABLE I : Comparison of generative circuit design methods.

Example: Generated Buck Converter
START TOPO_BUCK SEP
SPEC_VIN VAL_12.0 SPEC_VOUT VAL_5.0
SPEC_IOUT VAL_1.0 SEP
INDUCTOR VAL_100 $\mu$ H CAPACITOR VAL_22 $\mu$ F
RESISTOR VAL_5m $\Omega$ MOSFET VAL_15m $\Omega$
END

Fig. 2: Example ARCS-generated buck converter. Top : Token sequence with spec values and component values . Bottom : Decoded SPICE netlist fragment. The model generates the full sequence in

\sim

20 ms; grammar constraints ensure structural validity at each step.

Panel of Figure 4 — Fig. 3 : Grammar state machine for constrained decoding. At each autoregressive step, the current state determines which token types are valid, and a mask zeroes out all others before sampling. Topology -level constraints further restrict the allowed component types; Full constraints additionally restrict value ranges.

Method	Params	Struct	SimValid	Reward
Random Search	—	—	81.2%	7.28
Genetic Alg.	—	—	80.0%	7.48
Baseline GPT (SL)	6.5M	86.0 $\pm$ 1.9 %	40.1 $\pm$ 0.7 %	3.37 $\pm$ 0.06
Two-Head (SL)	6.8M	96.2 $\pm$ 1.0 %	50.4 $\pm$ 2.2 %	3.89 $\pm$ 0.09
Graph Trans. (SL)	6.8M	93.2 $\pm$ 1.4 %	45.4 $\pm$ 3.0 %	3.86 $\pm$ 0.15
REINFORCE (5000)	6.5M	95.5 $\pm$ 1.3 %	43.5 $\pm$ 1.2 %	3.74 $\pm$ 0.04

TABLE II : Unified comparison across all methods (160 conditioned specs, 10 per topology; autoregressive results averaged over 5 seeds with standard deviation). Search baselines have oracle access to the correct topology; ARCS generates from scratch.

Panel of Figure 6 — Fig. 4 : Simulation and structural validity across model variants (mean of 5 seeds). GRPO achieves the best sim-validity among autoregressive methods ( $+9.6$ pp over REINFORCE). Grammar-constrained decoding (GT+Constr) achieves 100% on both metrics.

Panel of Figure 7 — Fig. 5 : RL training dynamics (in-training validation; Table II reports held-out results). REINFORCE fluctuates around the SL baseline (dashed). GRPO steadily improves; the best checkpoint (step 500, 53.1% held-out) was selected via early stopping.

Method	Struct	SimSuccess	SimValid	Reward
VCG-only	100%	95.6%	85.3%	5.53
CCFM-only	100%	97.1%	85.3%	5.50
Hybrid (VCG+CCFM)	100%	97.1%	94.1%	6.37

TABLE III : Hybrid evaluation with SPICE-based ranking across VCG and CCFM sources (4 candidates/source; all 34 topologies). Hybrid picks the highest-reward candidate per topology. Note: the statistical evaluation in Table IV uses 50 samples on 32 topologies for a more rigorous comparison with baselines.

Method	SPICE Evals	Reward (95% CI)	SimValid
Random Search	1	5.18 [5.05, 5.31]	91.4%
Genetic Alg.	320	7.56 [7.53, 7.60]	100.0%
VCG only	1	5.34 [5.27, 5.42]	94.0%
CCFM only	1	5.51 [5.44, 5.58]	95.7%
Hybrid	8	6.43 [6.38, 6.48]	99.9%

TABLE IV : Publication evaluation with spec-aware reward (50 samples per topology, 32 topologies, bootstrap 95% CI). Reward measures both functional correctness and spec compliance (gain accuracy for amplifiers, cutoff accuracy for filters, frequency accuracy for oscillators). All pairwise comparisons significant at

p<0.001

(Wilcoxon signed-rank).

Variant	Struct	SimValid	Reward
ARCS + RL (full)	98.1%	52.5%	3.49
No RL (supervised only)	90.6%	46.9%	3.24
No spec conditioning	58.8%	38.8%	2.60
Tier 1 only (7 topos)	100%	20.6%	3.77

TABLE V : Ablation study (160 samples, baseline model).

Method	Reward	Sims	Time
ARCS only	5.45	3	0.8 s
GA cold-start	7.43	220	47.3 s
GA warm-start	7.18	113	19.7 s

TABLE VI : Warm-start comparison. GA-Warm uses ARCS-seeded initialization with 49% fewer SPICE simulations and 58% less wall time.

Level	Struct %	Comp %	Avg Comp	Time
None	0.0%	0.0%	—	269 ms
Grammar	100%	0.0%	18.6	125 ms
Topology	100%	100%	4.3	27 ms
Full	100%	100%	4.3	25 ms

TABLE VII : Constrained decoding results (random-init model, 50 samples across 32 topologies). Constrained decoding achieves 100% structural validity by construction and is faster than unconstrained sampling.

$N$	Conf.	SimValid	Reward	Time	Speedup
1	$-$ 1.16	72.5%	5.01	35 ms	1,680 $\times$
3	$-$ 0.82	85.0%	5.48	97 ms	606 $\times$
5	$-$ 0.74	85.0%	5.40	164 ms	359 $\times$
10	$-$ 0.67	77.5%	5.14	324 ms	181 $\times$
20	$-$ 0.57	82.5%	5.18	641 ms	92 $\times$
50	$-$ 0.52	82.5%	5.10	1.6 s	37 $\times$

TABLE VIII : Best-of-

N

scaling with a trained model (80 specs, Topology constraints). Model confidence (mean log-prob) improves monotonically; SPICE reward peaks at

N\!=\!3

. Even

N\!=\!50

costs only 1.6 s, still 37

\times

faster than random search.

Panel of Figure 14 — Fig. 6 : Inference-time scaling curve. Best-of- $N$ with model confidence ranking peaks at $N\!=\!3$ (reward 5.48, 97 ms), narrowing the gap to search baselines (RS 7.28 / 58.8 s, GA 7.48 / 271 s) at $>$ 600 $\times$ less cost. The plateau beyond $N\!=\!5$ reflects the misalignment between model confidence and SPICE reward.

Metric	Value
Pearson correlation ( $r$ )	0.988
Spearman rank corr. ( $\rho$ )	0.947
MAE	0.147
RMSE	0.390
Within $\pm$ 0.5	93.4%
Within $\pm$ 1.0	97.8%

TABLE IX : Learned reward model evaluation on 41K SPICE-simulated circuits. The model achieves

r\!=\!0.988

correlation with ground truth and 93.4% of predictions within

\pm

0.5 of the true reward.

	SL Generator			RL Generator
$N$	Conf	RM	$\Delta$ %	Conf	RM	$\Delta$ %
1	5.16	5.16	—	5.06	5.06	—
3	5.05	5.15	+2.0	5.08	5.18	+2.1
5	5.03	4.71	$-$ 6.5	5.12	5.16	+0.7
10	5.08	5.22	+2.7	5.30	5.16	$-$ 2.5
20	5.18	4.81	$-$ 7.2	5.04	5.17	+2.5

TABLE X : Best-of-

N

ranking comparison: confidence vs. learned reward model (80 trials per cell, 5 seeds

\times

16 test specs). The reward model consistently improves ranking at

N\!=\!3

(

+2.0

–

2.1\%

) for both SL and RL generators.

Appendix figures & tables1 asset

Supplementary material from the paper’s appendix.

Appendix

Topology	Cat	Reward	95% CI
current_mirror	B	8.00	[8.00, 8.00]
voltage_doubler	P	7.96	[7.96, 7.97]
shunt_regulator	R	7.77	[7.64, 7.85]
series_regulator	R	7.59	[7.41, 7.73]
sallen_key_lowpass	F	7.49	[7.36, 7.60]
common_emitter	B	7.05	[6.90, 7.20]

Appendix

TABLE XI : Per-topology hybrid-ranked results (50 samples, spec-aware reward).

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Electronic Design Automation uses algorithms and software to design, verify, optimize, and manufacture electronic circuits and systems.

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Automating analog circuit topology design is essential to reduce the extensive manual effort required to meet increasingly diverse and customized application demands. Recent advances have applied sequence-to-sequence fine-tuning on pretrained language models to directly generate circuit topologies from user specifications in a single pass. However, these one-shot generation methods failed to generate complex circuits due to their exponentially growing search spaces and limited training datasets. In this paper, we present EXPLORE, a search-enhanced framework that integrates simulator-guided Monte Carlo Tree Search (MCTS) with transformer-based decoding to enable test-time scaling for analog topology generation. By leveraging language-model priors and bypassing high-confidence structural tokens, EXPLORE allocates expensive simulator budget primarily toward topology-altering decisions during search. On a 6-component benchmark at a tight tolerance of 0.01, EXPLORE raises the success rate from 12% for one-shot generation and 33% for a sampling-and-filter baseline to 65%, and lowers MSE by over 20% relative to sampling-and-filter under the same search budget. These results establish EXPLORE as the first framework to integrate structured test-time search with LM decoding for analog topology generation, and a practical step toward scaling LLM-driven design automation.

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