OmniSch: A Multimodal PCB Schematic Benchmark For Structured Diagram Visual Reasoning

Taiting Lu; Kaiyuan Lin; Yuxin Tian; Mingjia Wang; Yubo Wang; Muchuan Wang; Sharique Khatri; Akshit Kartik

cs.CVMar 31, 2026

OmniSch: A Multimodal PCB Schematic Benchmark For Structured Diagram Visual Reasoning

Authors: Taiting Lu, Kaiyuan Lin, Yuxin Tian, Mingjia Wang, Yubo Wang, Muchuan Wang, Sharique Khatri, Akshit Kartik,

Organizations: Pennsylvania State University, USA · Independent Researcher · Shanghai Jiao Tong University, China · Binghamton University, USA ·

Abstract

Recent large multimodal models (LMMs) have made rapid progress in visual grounding, document understanding, and diagram reasoning tasks. However, their ability to convert Printed Circuit Board (PCB) schematic diagrams into machine-readable spatially weighted netlist graphs, jointly capturing component attributes, connectivity, and geometry, remains largely underexplored, despite such graph representations are the backbone of practical electronic design automation (EDA) workflows. To bridge this gap, we introduce OmniSch, the first comprehensive benchmark designed to assess LMMs on schematic understanding and spatial netlist graph construction. OmniSch contains 1,854 real-world schematic diagrams and includes four tasks: (1) visual grounding for schematic entities, with 109.9K grounded instances aligning 423.4K diagram semantic labels to their visual regions; (2) diagram-to-graph reasoning, understanding topological relationship among diagram elements; (3) geometric reasoning, constructing layout-dependent weights for each connection; and (4) tool-augmented agentic reasoning for visual search, invoking external tools to accomplish (1)-(3). Our results reveal substantial gaps of current LMMs in interpreting schematic engineering artifacts, including unreliable fine-grained grounding, brittle layout-to-graph parsing, inconsistent global connectivity reasoning and inefficient visual exploration.

Figures & tables

Figure 1: Large multimodal models fail to reliably perform core visual understanding tasks on structured schematic diagrams. Errors in component detection, topological connectivity reasoning, and spatial layout interpretation highlight persistent limitations in handling the compositional and relational complexity inherent in schematic diagrams.

Dataset	Images	Avg. Sym. Img	Symbol Cat.	BBox	Spatial Netlist	EDA Render Engine	Annotation				Year
							Symb.	Pin	Text	Net
CGHD [ 34 ]	2,424	42	45	✓	✗	✗	✓	✗	✓	B-Net	2021
AMSNet [ 32 ]	894	10	12	✗	✗	✗	✓	✗	✗	B-Net	2024
Masala-CHAI [ 11 ]	7,500	12	12	✗	✗	✗	✓	✗	✗	B-Net	2024
AMSNet 2.0 [ 30 ]	2,686	10	12	✗	✗	✗	✓	✗	✗	B-Net	2025
Image2Net [ 36 ]	2,914	15	22	✗	✗	✗	✓	✗	✗	B-Net	2025

Table 1: Comparison of publicly available schematic-to-netlist benchmarks and datasets. Abbreviations: Sch.—schematic diagram; Sp.Netlist—spatially weighted netlist.

Figure 2: Overview of OmniSch benchmark with representative cases.

Figure 3: Comparison between different data annotation paradigms. (a) Manual annotation: . Relying on human expert on labeling . (b) Auto annotation: Our OmniSch directly directly render schematic source code and automatically label data via our EDA rendering engine.

Panel of Figure 4 — Figure 4: Statistical overview of the OmniSch benchmark. The dataset encompasses a diverse range of electronic domains, comprising 1-440 symbols, 1-1200 pins, 1-400 nets, and 1-1600 text instances. This large-scale diversity provides a comprehensive benchmark for the automatic generation and evaluation of schematic netlists.

Figure 5: Synthesized schematic variations generated by our custom EDA generative rendering engine. The first diagram shows the original export from the industrial EDA tool; all remaining diagrams are rendered by our engine under controlled variations. (a) original EDA export; (b) full text; (c) without all text; (d) without symbol names and values.

Figure 6: Overview of the ReAct-based agentic framework for LMMs to evaluate usage and performance of LMMs using tools in schematic-to-netlist conversion.

Model	Size	Image Input	Symbol					Pin				Net		Graph		Geometric	Pass Rate
			Detection (F1)		Attribute			Detection (F1)		Attribute		Detection	Attribute	Structure		Structure
			Match by Eq. ( 1 )	Match by IoU	Name	Value	Type	Match by Eq. ( 2 )	Match by IoU	PinName	PadName	F1	NetName	IoU	1-GED	Kendall’s $\tau$	Pass
Commercial Chatbot Systems
GPT-5.2	-	Real	0.5276	0.0009	0.1761	0.2434	0.2948	0.5155	0.0003	0.1607	0.1780	0.1987	0.1822	0.1546	0.0945	0.0337	0.7097
		Real Low R.	0.3184	0.0032	0.0363	0.0566	0.0451	0.1756	0.0000	0.0641	0.0547	0.0612	0.0504	0.0480	0.0590	0.0170	0.9946
		Synth.	0.4732	0.0007	0.1460	0.2196	0.2600	0.5217	0.0003	0.2160	0.1738	0.2588	0.2445	0.1722	0.0944	0.0501	1.0000

Table 2: Evaluation reults of LMMs on single prompt zero-shot and Ablation Study schematic-to-netlist generation. Real denotes the schematic exported by industrial EDA; Synth. denotes the synthesis schematic by our custom EDA; GED denotes as graph edit distance. Symbol attributes (Name, Value, Type) are evaluated on matched symbol detections only, and pin attributes (PinName, PadName) are evaluated on matched pin detections only.

Model	Size	Setting	Symbol					Pin				Net
			Name	Name*	Value	Value*	Type	PinName	PinName*	PadName	PadName*	NetName
Commercial chatbot systems
GPT-5.2	-	w/o GT BBox	0.6948	0.6457	0.6610	0.6507	0.6886	0.7892	0.7621	0.2654	0.1298	–
		w/ GT BBox	0.8565	0.8482	0.8088	0.8252	0.8458	0.9056	0.8567	0.8426	0.9473	0.6926
		$\Delta$	+ $23.28$ %	+ $31.36$ %	+ $22.36$ %	+ $26.82$ %	+ $22.83$ %	+ $14.76$ %	+ $12.41$ %	+ $217.57$ %	+ $629.43$ %	–
GPT-5 Mini	-	w/o GT BBox	0.5539	0.5835	0.4983	0.4797	0.5292	0.6285	0.5545	0.1311	0.1138	–

Table 3: Evaluation results of agentic evaluation. w/o GT BBox denotes full-image search, where LMMs must first localize the target before performing visual search; w/ GT BBox denotes detector-assisted search, where an initial bounding box is provided and LMMs only expand it without re-localizing the target. Both input images are the generated schematic in Fig. 5 (d).

\Delta

denotes the relative improvement (%) of w/ GT BBox vs. w/o GT BBox ; * denotes metrics computed only on instances with visible text.

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OmniLayout: A Schematic-Coupled Multimodal Benchmark for Constraint-Aware Geometric Reasoning in PCB Layout

Taiting Lu, Kaiyuan Lin, Mingjia Wang, Haolin Ye+11

Pennsylvania State University · Shanghai Jiao Tong University · Independent Researcher+2

Electronic Design Automation Spatial Reasoning LLM Reasoning

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Recent large language models (LLMs) have demonstrated remarkable progress in 3D spatial reasoning, spatial grounding, and fine-grained geometric understanding. However, their ability to reason about densely packed object placement under strict spatial and functional constraints remains largely unexplored, despite being a fundamental challenge in practical electronic design automation (EDA) workflows. To bridge this gap, we introduce OmniLayout, the first benchmark designed to evaluate LLMs on printed-circuit-board (PCB) layout placement reasoning under real-world geometric, routing, and connectivity constraints. OmniLayout contains 1,681 industrial-grade schematic-coupled PCB layouts and includes four tasks: (1) geometric reasoning for IC physical placement, with 77.24K placement instances constrained within PCB board boundaries; (2) routability-aware placement reasoning, generating physically valid component placements; (3) electrical functionality, preserving schematic-specified connectivity and electronic functional correctness; and (4) tool-augmented agentic reasoning for invoking external tools to accomplish tasks (1)-(3). Our results reveal substantial limitations of current LLMs in PCB layout placement, including weak geometric reasoning, poor routability optimization, and inconsistent preservation of electrical functionality.

Abstract

Spatial Reasoning Benchmarks

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