Arch: An AI-Native Hardware Description Language for Register-Transfer Clocked Hardware Design

Shuqing Zhao

cs.PLApr 7, 2026

Arch: An AI-Native Hardware Description Language for Register-Transfer Clocked Hardware Design

Authors: Shuqing Zhao

Abstract

We present Arch (AI-native Register-transfer Clocked Hardware), a hardware description language for micro-architecture specification and AI-assisted code generation. Arch provides first-class constructs for pipelines, FSMs, FIFOs, arbiters, register files, buses with handshake channels, clock-domain crossings, and multi-cycle threads -- structures that existing HDLs express only as user-defined patterns prone to subtle errors. A central design choice is that clocks and resets are parameterized types (Clock<D>, Reset<S,P,D?>) rather than ordinary nets, converting CDC and reset-domain analysis from external linter passes into compile-time typing rules. Bit widths, port directions, single-driver ownership, and combinational acyclicity are tracked in the same pass, catching latches, width mismatches, loops, and unsynchronized crossings before simulation. A guard clause on reg declarations captures the valid-data pattern declaratively, catching the producer bug where a valid flag asserts before data is written. Every syntactic choice is governed by an AI-generatability contract: an LL(1) grammar, no preprocessor, a uniform declaration schema, named block endings, and a todo! escape hatch let LLMs produce structurally correct, type-safe Arch from natural-language specs without fine-tuning. The compiler emits lint-clean IEEE 1800-2017 SystemVerilog and auto-generates safety properties (FIFO no-overflow, counter range, FSM legal-state, handshake protocol) verified with Verilator -- assert and EBMC, plus direct AST-to-SMT-LIB2 bounded model checking via arch formal. An integrated simulator compiles designs to native C++ with Python cocotb support. Case studies: L1 cache and AXI DMA (Yosys/OpenSTA, Sky130); 428/431 tests pass on VerilogEval and CVDP.

Figures & tables

Type	Width	Notes
Bit	1 bit	Raw logic bit
UInt<N>	$N$ bits	Unsigned integer
SInt<N>	$N$ bits	Two’s complement signed
Bool	1 bit	Alias for UInt<1>
Clock<D>	1 bit	Domain-tagged clock
Reset<S,P,D?>	1 bit	Sync/Async; optional domain for RDC

Table 1: Arch primitive types

Component	Size	Purpose
Reference Card	${\sim}400$ lines	Construct catalog, schema, type table
Design Intent	5–20 lines	Natural-language block description
Compiler Output	5–30 lines	Structured error feedback

Table 2: AI context window components

Phase	Key Actions
Parse	Syntax, named-block matching
Elaborate	Parameter resolution, generic instantiation, type expansion
Resolve	Symbol table construction, cross-file name resolution
Type Check	Bit-width safety, clock-domain tracking, direction safety, single-driver rule
Lower	Pipeline hazard generation, FIFO implementation, arbiter logic, FSM encoding
Verify Emit	assert / cover $\to$ concurrent SVA with auto-generated safety properties; assume planned

Table 3: Compiler pipeline phases

SV Runtime Complexity	Arch Equivalent	Enables
Delta cycles (unbounded multi-pass convergence)	No combinational loops—static DAG	Bounded settle (1–2 passes), no fixpoint iteration
X/Z propagation (4-valued logic)	Structural X eliminated (no tri-state, single-driver rule, no implicit latches)	2-valued logic with runtime checks for residual sources ( Table 6 )
Multiple drivers (wired-OR resolution)	Single-driver rule at compile time	No resolution functions
Non-deterministic always ordering	Topological order from dataflow DAG	Deterministic simulation
Implicit latches	No implicit latches (compile error)	Static register allocation
Dynamic clock generation	Clock<D> typed, domain-verified	Static clock scheduling

Table 4: Language invariants enabling native compilation

Simulator	Model	Speed
Icarus Verilog [ 12 ]	Event-driven, interpreted, 4-state	$1\times$
Commercial sim. (compiled)	Compiled C, 4-state	${\sim}30$ – $100\times$
Verilator [ 9 ]	Cycle-acc. compiled C++, 2-state	${\sim}30$ – $100\times$ †
Arch native ∗	LLVM IR, 2-state	$50$ – $200\times$
Arch native + SIMD ∗	AVX-512 / NEON	$200$ – $1000\times$

Table 5: Simulation performance comparison

X Source	Status in Arch	Detection Mechanism
Multi-driver contention	Eliminated structurally	Single-driver rule (compile error)
Tri-state Z / high-Z contention	Eliminated structurally	Arch has no tri-state nets
Implicit latch with unknown enable	Eliminated structurally	No-implicit-latches rule (compile error)
Floating input ports / dangling wires	Eliminated structurally	Direction and connectivity type checks
Explicit ’x literal injection	Eliminated structurally	Arch has no X literal in the source language
Uninitialized non-reset registers	Runtime detection	--check-uninit flag traps first read of unwritten reg; the guard VALID_SIG clause refines this for the valid-data pattern

Table 6: X sources and Arch’s handling of each

Design Type	8 cores	32 cores
Single-domain, deep chain	$1.5$ – $2\times$	$2$ – $3\times$
Wide parallel array	$3$ – $5\times$	$5$ – $8\times$
Multi-domain balanced	$5$ – $7\times$	$10$ – $18\times$
Multi-domain + wide arrays	$6$ – $8\times$	$15$ – $25\times$
AI accelerator (full)	$7$ – $9\times$	$18$ – $30\times$

Table 7: Parallel simulation speedup

File	Purpose	Lines
FsmCacheCtrl.arch	Main controller FSM	380
L1DCache.arch	Top-level integrator	319
FsmAxi4Wb.arch	AXI4 writeback FSM	107
FsmAxi4Fill.arch	AXI4 fill FSM	91
ModuleLruUpdate.arch	Pseudo-LRU tree	60
PkgL1d.arch	Types and enums	49

Table 8: L1D cache source breakdown

Target	Metric	Value
Xilinx 7-series	Total LUTs	913
	Flip-flops (FDRE)	993
	Estimated LCs	586
Sky130 130nm	Total area	78,134 $\mu$ m 2
	Flip-flops	2,017

Table 9: AXI DMA synthesis results

Module	Style	Cells	FFs	MUXes
FsmMm2sMulti	FSM	805	109	33
ThreadMm2s (v1)	Thread	1431	97	429
ThreadMm2s (v2)	Thread	680	92	68
FsmS2mmMulti	FSM	1002	119	—
ThreadS2mm	Thread	4051	616	—

Table 10: Thread vs. FSM synthesis (Yosys synth -flatten )

Metric	Result
Problems solved	156 / 156 (100%)
Verilator-clean	154 / 156 (99%)
Total Arch lines	3,199
Total generated SV lines	4,518
Overall Arch/SV ratio	70.8% ( ${\sim}$ 29% shorter)

Table 11: VerilogEval v2 benchmark results

Category	$n$	Arch	SV	Ratio
Combinational	83	${\sim}$ 1,100	${\sim}$ 1,300	${\sim}$ 85%
Sequential	44	${\sim}$ 900	${\sim}$ 1,100	${\sim}$ 82%
FSM	29	${\sim}$ 1,500	${\sim}$ 2,400	${\sim}$ 63%
Total	156	3,199	4,518	70.8%

Table 12: Arch vs. generated SV line counts by category

Category	Spec	Edit	Total	Pass
cid002	29	65	94	94
cid003	78	0	78	78
cid004	44	0	44	44
cid007	39	0	39	39
cid016	31	1	32	32
Total	221	66	287	287 (100%)

Table 13: CVDP benchmark results by category (ARCH-relevant subset)

Benchmark	Problems	In-scope	Pass Rate ‡
VerilogEval v2	156	156	154 (99%) †
CVDP	302	287	287 (100%) §
Combined	458	443	441 (99.5%)

Table 14: Combined benchmark results

Feature	Arch	SV	VHDL	Chisel	SpinalHDL	Amaranth	Spade	Bluespec	TL-Verilog
First-class pipeline	✓	—	—	—	—	—	✓	— †	Partial ‡
Pipeline hazard mgmt	✓	—	—	—	—	—	—	Implicit	—
First-class FSM	✓	—	—	—	✓	—	—	— †	—
First-class FIFO	✓	—	—	—	—	—	—	—	—
First-class arbiter	✓	—	—	—	—	—	—	—	—
Hook (custom policy)	✓	—	—	—	—	—	—	—	—

Table 15: Comparison of hardware description languages

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