quant-phApr 9, 2026
SaveScalable Neural Decoders for Practical Fault-Tolerant Quantum Computation
Organizations: Department of Physics, Harvard University, Cambridge, MA 02138, USA · Harvard Quantum Initiative, Harvard University, Cambridge, MA 02138, USA
Abstract
Quantum error correction (QEC) is essential for scalable quantum computing. However, it requires classical decoders that are fast and accurate enough to keep pace with quantum hardware. While quantum low-density parity-check codes have recently emerged as a promising route to efficient fault tolerance, current decoding algorithms do not allow one to realize the full potential of these codes in practical settings. Here, we introduce a convolutional neural network decoder that exploits the geometric structure of QEC codes, and use it to probe a novel "waterfall" regime of error suppression, demonstrating that the logical error rates required for large-scale fault-tolerant algorithms are attainable with modest code sizes at current physical error rates, and with latencies within the real-time budgets of several leading hardware platforms. For example, for the Gross code, the decoder achieves logical error rates up to x below existing decoders - reaching logical error rates at physical error - with 3-5 orders of magnitude higher throughput. This decoder also produces well-calibrated confidence estimates that can significantly reduce the time overhead of repeat-until-success protocols. Taken together, these results suggest that the space-time costs associated with fault-tolerant quantum computation may be significantly lower than previously anticipated.
Figures & tables
Figure 1: Structure-aware neural decoding for quantum error correction. (a) Top: errors accumulate on data qubits; stabilizer measurements produce a spacetime syndrome (pattern of detection events); a decoder determines whether a logical error occurred; the logical state is protected. Bottom (neural network decoder): syndromes are embedded into -dimensional representations and processed by convolutional layers whose local structure respects the code geometry—3D convolutions for surface codes, generalized convolutions on the torus for bivariate bicycle (BB) codes—followed by a final convolution scattering to data qubits, pooling over the data qubits in each logical operator’s support, and a prediction head applied independently to each logical observable. (b) Error suppression on the BB code ( rounds). The logical error rate per logical qubit per cycle, , where is the number of minimal failure modes of weight , decomposes into two regimes: a steep waterfall ( ) where the numerous high-weight failure modes dominate at moderate physical error rates , transitioning to a distance-limited floor ( ) at very low noise. BP+OSD (orange, ) misses the waterfall entirely. (c) Accuracy–latency tradeoff at : Cascade (GPU inference on NVIDIA H200) spans a range of (amortized) latencies while achieving lower logical error rates than prior decoders (single-threaded CPU). Diamond markers show the reported single-shot latencies of BP+OSD [ 5 ] , Relay [ 12 ] , Tesseract [ 6 ] , and the ML decoder of [ 15 ] . Error bars indicate 95% credible intervals.
Figure 2: Distance scaling of BB code decoders under circuit-level depolarizing noise. (a–c) Logical error rate per logical qubit per round ( rounds) versus physical error rate for the , , and bivariate bicycle codes, respectively. Cascade achieves lower logical error rates than BP+OSD, Relay, and (where evaluable) Tesseract across all code sizes. (d) Accuracy vs. latency at for all three BB codes (timing reported for BB codes is amortized latency). We include the published results of a different ML decoder [ 15 ] for the and codes. For the code, we are unable to evaluate Tesseract due to its computational cost; BP+OSD is similarly intractable at lower noise levels.
Figure 3: Distance scaling of surface code decoders at under circuit-level depolarizing noise. (a) Logical error rate per round versus code distance for MWPM, correlated MWPM, Tesseract, and Cascade. All decoders exhibit exponential error suppression ( ), with Cascade and Tesseract achieving the steepest slopes. (b) Accuracy–latency trade-off across code distances (GPU inference on NVIDIA H200). Amortized latency (dashed lines, batched inference) is significantly lower than the single-shot latency (solid lines, unbatched inference). (c) Error suppression factor extracted from exponential fits to panel (a).
Figure 4: Error suppression improves with model capacity. (a) Logical error rate versus memory error rate at distance for surface code models with varying hidden dimension (data-level depolarizing noise, used here for training efficiency). Larger models achieve lower error rates across the full range of noise levels. (b) Error suppression exponent for memory errors (from fitting ) versus hidden dimension. Small models ( ) exhibit poor scaling exponents well below reference decoders (MWPM, correlated matching), while large models ( ) approach optimal performance.
Figure 5: Confidence-aware decoding with the ML decoder on the bivariate bicycle code. (a) Logical error rate per cycle as a function of acceptance rate at . Our decoder (blue) achieves much steeper error suppression (as a function of acceptance rate) compared to cluster-based post-selection methods [ 48 ] (pink). (b) Logical error rate versus physical error rate for different discard rates. (c) Reliability diagram showing calibration across physical error rates (color scale); alignment with the diagonal indicates well-calibrated predictions.
Extended Data Fig. 1: Bottleneck residual block. The network backbone consists of identically-structured blocks with independent learned parameters, each processing a hidden representation of dimension at every syndrome location. First, the representation is projected from to dimensions (reduce); the code-specific convolution then operates in this lower-dimensional space (message passing), after which the representation is projected back to dimensions (restore). The bottleneck reduces the cost of the convolution by roughly while preserving expressive capacity. Each projection and convolution is preceded by batch normalization (BN), which standardizes activations to zero mean and unit variance, and a SiLU nonlinearity. A scaled residual connection adds the block input directly to the output, weighted by , so that each block learns a correction to the identity mapping rather than reconstructing the full representation—a standard technique for stable training of deep networks.
Extended Data Fig. 2: Architectural ablation on surface codes. (a) Architectural inductive biases visualized on 2D syndrome grids. Convolution : Arrows from two different positions show identical directional patterns (colors encode direction-specific learned weights), demonstrating translation equivariance combined with learned anisotropy. Local attention : Arrow thickness represents learned attention weights; different thickness patterns at different positions show the architecture is position-dependent rather than translation-equivariant. Full attention : Global all-to-all connectivity with position-dependent learned weights. (b) Logical error rate versus training compute (PFLOPs) for three architectures with fixed depth ( ) and width ( ) at distance , evaluated at physical error rate . Convolution achieves the lowest error rate, while local attention and full attention saturate at higher error rates despite equal or greater training compute. Existing decoders (MWPM, Correlated MWPM, Tesseract) shown for reference.
Extended Data Fig. 3: Block decomposition across architectures. Every block decomposes into two pointwise projections (grey) and one spatial operation (orange), differing only in their ordering and the dimension at which each operates. Trapezoids indicate dimension changes; rectangles indicate same-dimension operations; shape width encodes the channel dimension at each stage. The bottleneck contracts to before the spatial step; ConvNeXt and transformer blocks apply the spatial operation at full width followed by an expand–contract MLP. Under the relabeling , all three variants yield the same MAC cost structure ( Eq. 3 ). Pointwise nonlinearities and normalizations are omitted from the diagram as their cost is negligible compared to the linear projections and spatial operations.
Extended Data Fig. 4: Roofline latency per syndrome round on an AMD Versal AI Core FPGA (133 TOPS INT8). Solid lines: standard convolution; dashed lines: depthwise convolution. Both panels assume network depth and bottleneck factor . (a) Surface codes with ( kernel) and detectors per round. (b) Bivariate bicycle codes with (two bipartite steps of 12 neighbors each) and equal to the number of physical qubits. The horizontal dotted line marks the s-per-round budget for superconducting qubits. Latency scales as for other hardware targets: a TPU v1 (92 TOPS) or Edge TPU (4 TOPS) would shift all curves upward by or , respectively.