Generative Design for Direct-to-Chip Liquid Cooling for Data Centers

The emerging of large language models (LLMs) has posed significant challenges to the thermal management of data center. Intense GPU computation for LLMs results in localized hotspots. Moreover, spiking thermal loads during training and inference bursts make real-time cooling response more difficult to predict and control. Thermal-aware capacity planning of data center requires massive expensive high-fidelity CFD simulations. AI models can perform real-time prediction for unseen designs. However, existing works either have large prediction error, or have over-simplified assumptions for data center operations. This work presents an AI-driven framework that can perform thermal-aware capacity planning for a real-world data center in seconds. The embedded AI model learns from numerous key parameters (rack power, server power, server placement, HVAC settings etc.), and provides temperature prediction within milliseconds. This AI model is tested against high-fidelity CFD simulations, and results show that for unseen data center designs, model can achieve high accuracy with 10000X speedup. Driven by the AI model, the authors design the thermal-aware capacity planning framework. This framework can help data center designers and operators instantaneously optimize both workload distribution and HVAC cooling efficiency.

Chip placement plays an important role in physical design. While generative models like diffusion models offer promising learning-based solutions, current methods have the following limitations: they use random synthetic data for pre-training, require long sampling times, and often result in overlaps due to their dependence on gradient-based solvers during the sampling process. To overcome these issues, we propose FlowPlace, which features mask-guided synthetic data generation, flow-based efficient training with flexible prior injection, and hard constraint sampling for overlap-free layouts. Experiments on OpenROAD and ICCAD 2015 benchmarks show FlowPlace achieves better PPA metrics, 10-50$\times$ faster sampling efficiency, and zero overlaps.

Thermodynamic computing is an emerging hardware paradigm, in which stochastic physical dynamics serve as the direct computational primitive. The recent explosion of generative AI has only sharpened the search for alternative approaches to compute, and, as we show in this work, thermodynamic computing turns out to be well suited to this space. An important class of methods realises a function as the stationary expectation of an ergodic stochastic process: the answer is encoded in the time-averaged statistics of an equilibrating trajectory. To date, this equilibration-style class has been formulated exclusively through Langevin dynamics, restricting its implementations to analogue substrates and the engineering challenges those bring. In this work, we propose a substrate-independent formalisation of the equilibration-style formulation, in which the only object of design is the dynamical generator L* of an arbitrary ergodic process. The formalisation makes three hardware-level properties of the formulation explicit: the precision of a result is a knob set by how long the dynamics are run, sample averages decompose across independent trajectories, and dependent stages of a computation operate concurrently rather than serially, a property we call sequential parallelism. We instantiate the formalisation by fabricating a prototype digital thermodynamic computing chip, named CN101, that implements the formulation through discrete accumulator dynamics on standard CMOS using stochastic computing principles. We characterise CN101's success across conventional generative AI workloads in the form of VAEs and flow matching, applied to both image generation and scientific problems. Together, the formalisation and its digital instantiation show that the equilibration-style formulation is substrate-independent, and that its computational properties can be exploited on standard digital hardware.