Analog optical computers promise large efficiency gains for machine learning inference, yet no demonstration has moved beyond small-scale image benchmarks. We benchmark the analog optical computer (AOC) digital twin on mortgage approval classification from 5.84 million U.S. HMDA records and separate three sources of accuracy loss. On the original 19 features, the AOC reaches 94.6% balanced accuracy with 5,126 parameters (1,024 optical), compared with 97.9% for XGBoost; the 3.3 percentage-point gap narrows by only 0.5pp when the optical core is widened from 16 to 48 channels, suggesting an architectural rather than hardware limitation. Restricting all models to a shared 127-bit binary encoding drops every model to 89.4--89.6%, with an encoding cost of 8pp for digital models and 5pp for the AOC. Seven calibrated hardware non-idealities impose no measurable penalty. The three resulting layers of limitation (encoding, architecture, hardware fidelity) locate where accuracy is lost and what to improve next.
Figures & tables
Split
Samples
Unique groups
Class balance
Train
1,524,335
∼ 1,042,361
50.0 / 50.0%
Validation
191,838
∼ 130,295
50.3 / 49.7%
Test
190,607
∼ 130,295
49.8 / 50.2%
Table 1: Group-split dataset. All splits are near class-balanced.
Model
Features
Parameters
Optical
Test BACc (%)
XGBoost
19 raw
∼ 31,500
—
97.91±0.00
MLP-large
60 (one-hot)
24,578
—
97.46±0.04
MLP-small
60 (one-hot)
5,378
—
97.21±0.17
Ens-4x-AOC-48
60 (Ising)
21,510
9,216
95.14±0.46
Ens-4x-AOC-16
60 (Ising)
5,126
1,024
94.64±0.53
Ens-4x-AOC-16 (SimpleCell)
60 (Ising)
5,122
—
93.85±1.58
Table 2: Test balanced accuracy on 190,607 held-out mortgage applications, raw features (mean ± std over 3 seeds). Optical parameters are the subset executed on analog hardware.
Figure 1: Error-set overlap on raw features (XGBoost seed 42 vs AOC seed 0). XGBoost makes 3,971 errors; the AOC makes 9,792; only 3,577 are shared (Jaccard =0.351 ). On binarised features (Figure 2 ) the same pair shares over 90% of its errors (Jaccard =0.834 ). Binarisation collapses model diversity along with accuracy.
Model
Raw BACc (%)
Binarised BACc (%)
Δ (pp)
XGBoost
97.91
89.51
−8.40
MLP-large
97.46
89.57
−7.89
MLP-small
97.21
89.56
−7.65
Ens-4x-AOC-16
94.64
89.43
−5.21
Logistic regression
70.04
76.54
+6.50
Table 3: Effect of binarisation (mean over 3 seeds). All models evaluated on the same 190,607 test samples.
Figure 2: Error-set overlap on binarised features. Each model makes roughly 20,000 errors; 18,304 are shared (Jaccard =0.834 ). The models disagree on just 1.92% of the test set, having saturated the encoding ceiling.
Figure 3: Raw vs. binarised balanced accuracy for all model families. Binarisation costs 7.7 – 8.4pp for digital models and 5.2pp for the AOC. Logistic regression gains +6.5pp because one-hot binning linearises the feature space.
Figure 4: Decomposition of the accuracy gap between raw-feature XGBoost ( 97.9% ) and the binarised AOC ( 89.4% ). Architecture accounts for 3.3pp , encoding for 5.2pp , and hardware non-idealities for ∼0pp .
Figure 5: Balanced accuracy vs. parameter count. Filled circles: raw features; open squares: binarised. On raw features, AOC-16 and MLP-small have similar parameter counts ( ∼5,200 ) but a 2.6pp gap. In the binarised setting, all nonlinear models collapse to 89.4 – 89.6% regardless of capacity.
Sparse Mixture-of-Experts (MoE) models enable efficient scalability by activating only a small sub-set of experts per input, yet their massive parameter counts lead to substantial memory and energy inefficiency during inference. Analog in-memory computing (AIMC) offers a promising solution by eliminating frequent data movement between memory and compute units. However, mitigating hardware nonidealities of AIMC typically requires noise-aware retraining, which is infeasible for large MoE models. In this paper, we propose a retraining-free heterogeneous computation framework in which noise-sensitive experts, which are provably identifiable by their maximum neuron norm, are computed digitally while the majority of the experts are executed on AIMC hardware. We further assign densely activated modules, such as attention layers, to digital computation due to their high noise sensitivity despite comprising a small fraction of parameters. Extensive experiments on large MoE language models, including DeepSeekMoE and OLMoE, across multiple benchmark tasks validate the robustness of our approach in maintaining accuracy under analog nonidealities.
Mohammed Nowaz Rabbani Chowdhury, Hsinyu Tsai, Geoffrey W. Burr +3
Analog in-memory computing (AIMC) speeds up neural-network inference by doing the arithmetic directly inside a memory array, instead of shuttling weights back and forth between memory and a processor. This saves energy, but the physical devices that store the weights are imperfect: programming errors, electrical noise, limited-resolution converters, and outright broken cells all distort the computation, and every physical chip is distorted in its own way. A designer with several such chips available faces an uncomfortable choice: run all of them and combine the answers (safe, but wasteful of energy), or trust a single chip blindly (cheap, but with no guarantee on how often it is wrong). This paper introduces RACE-AIMC (Risk-Aware Certified Ensemble for AIMC), a framework that resolves this choice with statistics rather than guesswork. Offline, RACE-AIMC studies a pool of physical accelerators, picks the single best one for a given energy budget, and computes a mathematically exact upper bound on how often that accelerator will be wrong when it chooses to answer. Online, only that one accelerator is switched on; a lightweight check decides whether to accept its answer or defer to a fallback. In our simulations using a noisy weight mapping and multiple independent test runs, every certified bound stayed under a 10% error target (mean bound 7.83% +- 0.89%, with 70.88% +- 0.98% of inputs answered directly). The resulting system matches the accuracy of a clean digital baseline while cutting modeled energy use by 69.02% relative to always running every accelerator in the pool.
Analog in-memory computing is a promising platform for on-device execution of large language models because it performs matrix--vector multiplications (MVMs) in memory and in parallel, reducing data movement. However, limited digital-to-analog converter precision, input noise, and finite conductance states can degrade model accuracy, while full-model retraining to address these effects can be costly. We develop an optimizer-agnostic, parameter-efficient adaptation method based on Low-Rank Adaptation (LoRA), keeping the pretrained weights stored on analog arrays fixed while training the LoRA weights to adapt to downstream tasks and hardware non-idealities. Reliable adaptation requires handling errors in both forward and backward MVMs and physical weight updates. We use input reshaping to reduce input-induced MVM errors and update accumulation to retain small updates before programming them to finite-state analog devices. Across Llama-3.2-1B-Instruct and Llama-3-8B with both Muon and AdamW, input reshaping improves analog LoRA fine-tuning under noisy MVM computation. Update accumulation separately preserves sub-threshold updates and substantially improves adaptation under finite-resolution programming, including configurations with as few as 20 conductance states. Additional experiments show consistent held-out negative log-likelihood improvements across noisy analog settings.