Taming Asynchronous CPU-GPU Coupling for Frequency-aware Latency Estimation on Mobile Edge
Authors: Jiesong Chen, Jun You, Zhidan Liu, Zhenjiang Li
Organizations: Department of Computer Science, City University of Hong Kong, Hong Kong, China · INTR Thrust, System Hub, The Hong Kong University of Science and Technology (Guangzhou), Guangzhou, China
Precise estimation of model inference latency is crucial for time-critical mobile edge applications, enabling devices to calculate latency margins against deadlines and trade them for enhanced model performance or resource savings. However, the ubiquity of Dynamic Voltage and Frequency Scaling (DVFS) renders traditional static profiling invalid in real-world deployments, as inference latency fluctuates with varying processor (CPU and GPU) frequencies. While extensive profiling across frequency combinations is theoretically possible, it is prohibitively expensive, particularly for emerging Small Language Models (SLMs), where variable context lengths explode the profiling up to days. We observe that simple analytic scaling fails to predict these fluctuations due to the complex asynchronous coupling between CPU (kernel launching) and GPU (execution). In this paper, we introduce FLAME to accurately estimate inference latency across frequency combinations. It features a novel layer-wise modeling that quantifies the overlapping parallelism and then aggregates dynamic pipeline bubbles caused by asynchronous processor interactions when extending to the full model. This bottom-up approach ensures generalizability across diverse models from DNNs to SLMs, and its precise modeling allows for profiling a sparse subset of samples, cutting DNN profiling from hours to minutes and SLM profiling from days to mere minutes, while maintaining small estimation errors across frequencies. We further showcase FLAME's utility in a deadline-aware DVFS, outperforming the state-of-the-art approach in both power efficiency and latency guarantees.
Figures & tables
Fig. 1: Dynamic timing factor Δℓ(fc,fg) , denoted as Δℓ in the above figure for clear illustration, exists when a mobile edge device processes any model layer ℓ due to asynchronous interaction between its CPU and GPU. This asynchrony leads to (a) overlapping and (b) idle waiting between the CPU and GPU execution times.
Model
Time
Model
Time
ResNet50
43 min
GPT2-large
113 h
VGG16
54 min
Qwen2-1.5B
151 h
DenseNet121
102 min
Qwen2-7B
304 h
TABLE I: Overhead of exhaustive profiling for DNN and SLM models on NVIDIA Jetson AGX Orin.
Fig. 2: CDF of the ratio between the duration of the timing factor Δℓ(fc,fg) and the execution latency of the corresponding entire layer.
Fig. 3: Latency estimation error of existing methods for (a) DNN models and (b) SLM models.
Fig. 4: System architecture of FLAME.
Fig. 5: CDF of estimating independent (a) CPU and (b) GPU times for constituent layers.
Fig. 6: The selected top-10 HPCs most relevant to the inference latency of the convolution layer.
Fig. 7: Estimation error of (a) each layer in ResNet50 and (b) one layer in GPT2-large across context lengths.
Fig. 9: Estimated (Est) model-wise latency of FLAME compared to the ground truth (GT) across all frequency combinations for (a) ResNet50 and (b) GPT2-large.
Fig. 10: Deadline-aware DVFS vs. other strategies.
Figure 12Figure 13Figure 14
Fig. 20: Varying deadlines with (a) ResNet50 and (b) GPT2-large. The rate achieved (blue) higher than the required rate (red) means deadline requirement is met.
Fig. 21: Online adaptation for (a) ResNet50 and (b) GPT2-large with concurrent workloads.
Model
Time
Model
Time
ResNet50
2 min (43 min)
GPT2-large
2 min (113 h)
VGG16
3 min (54 min)
Qwen2-1.5B
2 min (151 h)
DenseNet
6 min (102 min)
Qwen2-7B
4 min (304 h)
TABLE II: Profiling overhead of FLAME. The numbers in parentheses are the time needed for full profiling.
Edge inference runs trained AI models on nearby devices such as phones, cameras, robots, and embedded computers under tight resource and latency limits.
Deploying Large Language Models (LLMs) directly on mobile platforms at the edge is gaining traction due to a myriad of benefits, such as increased privacy, personalization, and reduced latency. However, LLMs have heavy computational requirements, which are difficult for resource-constrained mobile and edge platforms to fulfill. In addition to limited compute resources, mobile and edge systems often have a compact form factor and lack physical mechanisms to dissipate heat generated from high processor usage rates (e.g., fans) to prevent throttling and reduced processing power, which LLMs can easily cause. To mitigate these effects, prior works have proposed various power governing strategies, such as dynamic voltage and frequency scaling (DVFS), for reducing power and heat generation for heavy computational tasks on mobile platforms. Recently, DVFS methods tailored for mobile LLMs have also been proposed. However, these methods mostly focus on optimizing hardware parameters and processor frequencies, and they fall short under some thermally constrained scenarios. Drawing from recent advances in machine learning, we identify and take advantage of the key insight that not all tokens require full-depth inference to maintain high-quality generation. Motivated by this, we present PELM, a solution that augments traditional DVFS processor frequency tuning with two additional workload-specific knobs: 1) speculative decoding and 2) variable verification depth to expand the optimization space to multiple dimensions for more power efficient on-device LLM inference. In extensive evaluations across hardware platforms and datasets, PELM demonstrates superior performance compared to state-of-the-art power governing methods, with up to 23.1% speedup and 52.4% reduction in energy consumption, while maintaining comparable task performance. The source code is available at https://github.com/imec-nu/PELM.
The rapid scaling of Large Language Models (LLMs) has significantly increased computational cost, energy consumption, and inference latency, making accurate estimation essential for sustainable artificial intelligence deployment and hardware-aware design. In this work, we introduce Hybrid Modeling for Energy and Latency of LLMs (HYMELL), a hybrid three-level framework for estimating LLM inference latency and energy by combining analytical modeling with machine learning (ML). HYMELL models LLM execution through a three-level hierarchy: analytical estimation of primitive operations, ML prediction of higher-level components, and an end-to-end model that captures system-level overheads across both prefill and decode phases. The framework supports diverse architectures, including dense and mixture-of-experts (MoE) feed-forward networks (FFNs), as well as multi-head attention (MHA) and grouped-query attention (GQA) mechanisms. Evaluated on an NVIDIA H100 graphics processing unit (GPU), HYMELL achieves high predictive accuracy; notably, for LLaMA 3 8B, it attains less than 5% error for both prefill and decode phases. By predicting execution costs directly from architectural parameters, it enables fast, hardware-free design space exploration and energy-efficient optimization.
Saeid Shokoufa, Mohammad Erfan Sadeghi, Mehdi Kamal +1
University of Southern California Los Angeles, California, USA
Edge devices are increasingly utilized for deploying deep learning applications on embedded systems. The real-time nature of many applications and the limited resources of edge devices necessitate latency-targeted neural network compression. However, measuring latency on real devices is challenging and expensive. Therefore, this letter presents a novel and efficient framework, named EvoLP, to accurately predict the inference latency of models on edge devices. This predictor can evolve to achieve higher latency prediction precision during the network compression process. Experimental results demonstrate that EvoLP outperforms previous state-of-the-art approaches by being evaluated on three edge devices and four model variants. Moreover, when incorporated into a model compression framework, it effectively guides the compression process for higher model accuracy while satisfying strict latency constraints. We open source EvoLP at https://github.com/ntuliuteam/EvoLP.
Shuo Huai, Hao Kong, Shiqing Li +5
School of Computer Science and Engineering, Nanyang Technological University, Singapore · HP-NTU Digital Manufacturing Corporate Lab, Nanyang Technological University, Singapore · HP Inc., Palo Alto, California, USA