A Spiking Sequence Generator for Polar Trajectories on Neuromorphic Hardware
Authors: William R. P. Nourse, Roger D. Quinn
Organizations: Mechanical & Aerospace Engineering, Case Western Reserve University, Cleveland, OH, USA · Mechanical & Aerospace Engineering, West Virginia University, Morgantown, WV, USA
Neuromorphic controllers for size, weight, and power-constrained systems require neural architectures that are both energy-efficient and interpretable at the level of system dynamics. However, existing approaches either rely on end-to-end trained spiking networks with limited interpretability, or on converted classical controllers that fail to fully exploit neuromorphic dynamics. We present a spiking neural network (SNN) architecture for generating polar trajectories, using a winner-take-all (WTA) architecture with accessory populations that induce controlled transitions in neural activity. We demonstrate tuning rules for these population dynamics, and utilize a form of shunting inhibition to enable independent control of direction, speed, and radius of the resulting polar trajectories. We implement the network on the SpiNNaker2 neuromorphic processor, and demonstrate a two to three orders of magnitude reduction in wall-clock step time and three to four orders of magnitude reduction in energy expenditure when compared to conventional computing platforms.
In biological circuits, sequential neural activity evolves along dynamic, low-dimensional manifolds to enable flexible behavior. Spiking network models link aspects of this sequential activity to features of manifold geometry through specific circuit mechanisms, making dynamic neural manifolds parameterizable, and thereby offering an explainable framework for neural computation. Extending this framework to neuromorphic engineering, we present an implementation on the SpiNNaker 2 chip for real-time, closed-loop control. By allowing sensory inputs to modulate heterogeneous inhibition, gain, and transient currents, our architecture drives rapid subspace rotations to switch between behaviors, as well as fine-grained trajectory control within them. We validate this via a robotic simulation where an agent uses sensory feedback to dynamically reconfigure its manifold geometry to navigate through a maze. Our results establish dynamic manifolds as a feasible approach for explainable neuromorphic architectures and a substrate for investigating biological neural dynamics.
Spiking Neural Networks (SNNs) coupled with neuromorphic hardware offer energy-efficient solutions for humanoid robot control. However, existing SNN-based motor control systems address bipedal locomotion and arm control in isolation, leaving integrated control of both unaddressed. We present a spiking architecture that coordinates force-based arm control and bipedal locomotion in a simulated humanoid, using the Neural Engineering Framework (NEF) and Semantic Pointer Architecture (SPA). High-level action selection between locomotor and arm control is mediated by a biologically grounded spiking basal ganglia model. We validate the system through co-simulation of Nengo, for the neural control, and Isaac Sim, demonstrating successful target reaching, continuous digit drawing, path-following locomotion, and finally, switching between walking and arm control via basal ganglia disinhibition. To our knowledge, this is the first integrated spiking controller to combine bipedal locomotion and arm control on a full-scale humanoid platform. The full spike-based implementation enables future deployment on low-power neuromorphic hardware.
Spiking neural networks (SNNs) provide event-driven and low-power computation inspired by biological neural systems, but current implementations rely on von Neumann graphics processing units (GPUs) and central processing units (CPUs) platforms, where memory and computation bottlenecks limit energy efficiency. To address this challenge, this paper proposes an analog memristor-based spiking neural network (SNN) accelerator that integrates in-memory synaptic computation with analog integrate-and-fire (IF) neurons, eliminating multi-transistor CMOS synapse circuits and enabling asynchronous event-driven operation at the 45nm technology node. Additionally, a digital SNN accelerator is designed and optimized at the 5 nm technology node for comparison. The proposed architecture is evaluated using a predator-prey tracking task that emulates pursuit behavior. In this task, the analog SNN accelerator's inference closely matches the ideal software inference with a mean squared error (MSE) of 0.004. HSPICE simulation results show that the proposed analog SNN accelerator achieves 12.7 times lower energy consumption and 1.26 times lower delay compared to the digital baseline, demonstrating the potential of memristor-based neuromorphic circuits for energy-efficient real-time edge intelligence.