PPAPlace: Differentiable Cross-Stage Objectives for Chip Placement Optimization

Ruogu Chen; Jie Han

cs.LGAug 13, 2026

PPAPlace: Differentiable Cross-Stage Objectives for Chip Placement Optimization

Authors: Ruogu Chen, Jie Han

Organizations: University of Alberta Department of Electrical and Computer Engineering Edmonton, AB, Canada

Abstract

Macro placement significantly affects a chip's post-route performance, power, and area (PPA). Most placement methods optimize half-perimeter wirelength (HPWL) as the primary objective. However, recent benchmarking shows a near-zero correlation between HPWL and post-route timing metrics such as the worst negative slack (WNS) and total negative slack (TNS). As a result, all six evaluated artificial intelligence (AI) placers degraded PPA relative to the hierarchical baseline. Recent efforts have tried to train cross-stage predictors to close this gap. However, existing methods focus on macro-only representations and use pre-route metrics as training labels. A label fidelity study of ten circuits at four design flow stages reveals that HPWL and pre-route timing poorly reflect final post-route timing rankings. In contrast, post-global-routing achieves the best balance between final timing fidelity and label generation cost-effectiveness. Based on this finding, PPAPlace is a timing-driven differentiable surrogate predicting post-route PPA from macro and standard-cell placements. The surrogate is a dual-stream predictor that combines graph attention over the chip netlist with spatial convolution over the placement grid. It is trained on post-global-routing labels. The predicted WNS and TNS gradients flow end-to-end back to cell coordinates. PPAPlace exploits these gradients in two ways: as a co-objective injected into an analytical placer's optimization loop (PPAPlace-CoOpt), and as a post-placement refinement step that adjusts macro positions via projected gradient descent (PPAPlace-Refine). On five ChiPBench test circuits excluded from training, PPAPlace improves average WNS and TNS by 22% and 51% over the hierarchical baseline while preserving power and routability, using the same predictor without test-circuit retraining. Code is available at https://github.com/ValleyC/PPAPlace.

Figures & tables

Stage	bp_be	bp_fe	bp_be12	isa_npu	swerv	vga_lcd	ether	dft68	mor1kx	ari133	Avg	Time
	(10)	(11)	(12)	(15)	(28)	(62)	(64)	(68)	(78)	(132)		(hrs)
HPWL	+.12	$-.15$	+.08	$-.21$	+.05	$-.18$	$-.09$	+.14	$-.11$	+.03	$-.03$	$<$ 0.01
Pre-CTS STA	+.15	+.09	$-.07$	+.18	$-.11$	+.06	$-.14$	+.22	+.03	+.12	+.05	0.08
Post-CTS	.83	.64	.71	.38	$-.12$	.25	$-.31$	.47	.19	.77	.38	0.14
Post-GRT	.80	.91	.87	.85	.89	.82	.78	.84	.86	.94	.86	0.20

Table 1. Spearman

\rho_{\text{WNS}}

between intermediate and post-route timing across ten ChiPBench circuits (macro count in parentheses). Green :

\rho\geq 0.7

; light :

0.3\leq\rho<0.7

; pink : negative.

\rho_{\text{TNS}}

follows the same pattern. Rightmost column: average wall-clock cost of generating one label at each stage, shown on a blue scale to distinguish it from correlation. CTS: clock-tree synthesis; DRT: detailed routing. Post-DRT is the correlation reference (

\rho\equiv 1

3.7

hrs on average).

Figure 1. PPAPlace framework. (a) Offline training on post-GRT labels. (b) CoOpt: surrogate gradients injected into DREAMPlace as a co-objective. (c) Refine: post-placement gradient descent on the converged result.

Prior placement methods
	swerv_wrap			ariane133			black_parrot			bp_be			ariane136			Average
Method	WNS	TNS	Cong	WNS	TNS	Cong	WNS	TNS	Cong	WNS	TNS	Cong	WNS	TNS	Cong	WNS	TNS	Cong
Hier-RTLMP ( Kahng et al., 2024 )	1.00	1.00	1.00	1.00	1.00	1.00	1.00	1.00	1.00	1.00	1.00	1.00	1.00	1.00	1.00	1.00	1.00	1.00
DREAMPlace ‡ ( Lin et al., 2019 )	1.13	0.93	1.04	2.90	0.61	0.98	0.94	1.82	1.05	0.87	0.86	1.06	2.23	5.37	0.94	1.61	1.92	1.01
DREAMPlace 4.0 ( Liao et al., 2022 )	1.02	0.88	1.05	1.65	0.58	0.99	0.91	1.30	1.06	0.82	0.83	1.08	1.45	2.85	0.96	1.17	1.29	1.03
AutoDMP ‡ ( Agnesina et al., 2023 )	1.43	1.47	1.09	1.44	1.76	0.91	1.01	0.85	1.06	0.49	1.03	1.18	1.62	3.69	0.94	1.20	1.76	1.04

Table 2. Post-route timing and global-routing wire-density congestion, each normalized per circuit by Hier-RTLMP (lower is better). PPAPlace rows report mean

\pm

std over 3 independently seeded runs; baselines are deterministic or from published results. Bold : best; underline : second best. † : from ( Geng et al., 2025 ) ; ‡ : from ChiPBench ( Wang et al., 2025 ) ; § : ratios computed from ( Shi et al., 2026 ) (same OpenROAD flow; std-cell placement differs).

Figure 2. Placement comparison on swerv_wrapper : (a) Hier-RTLMP, (b) DREAMPlace, (c) PPAPlace-CoOpt+Refine.

Figure 3. (a) Per-circuit normalized WNS (Table 2 ). (b) True vs. surrogate WNS during gradient refinement on swerv_wrapper.

	swerv	ari133	black	bp_be	ari136	Avg.
cos( $\nabla$ WNS)	0.49	0.58	0.51	0.62	0.43	0.53
cos( $\nabla$ TNS)	0.43	0.49	0.46	0.53	0.37	0.46

Table 3. Cosine similarity between surrogate gradient and true post-GRT PPA change (100 perturbation directions per circuit).

Held-out (DREAMPlace)
Metric	swerv	ari133	black	bp_be	ari136	bp_fe t	ether t	Avg.
$\rho$	0.74	0.81	0.77	0.83	0.72	N/A	N/A	0.77
$\tau$	0.56	0.62	0.55	0.65	0.51	N/A	N/A	0.58
Top-5	60%	80%	60%	80%	60%	N/A	N/A	68%
Cross-placer (RTLMP)
$\rho_{\text{WNS}}$	0.63	0.58	0.60	0.72	0.54	0.68	0.55	0.61

Table 4. Surrogate generalization: ranking accuracy on held-out placements and cross-placer transfer to RTLMP.

Figure 4. (a) Leave-one-circuit-out (LOCO) cross-circuit generalization (Kendall’s

\tau

). (b) Predictor architecture ablation (Kendall’s

\tau

	superblue16		superblue18
Method	WNS	TNS	WNS	TNS
DREAMPlace ( Lin et al., 2019 )	$-107.05$	$-1526.10$	$-88.11$	$-751.27$
WireMask-EA ( Shi et al., 2023 )	$-635.89$	$-18343.30$	$-78.25$	$-406.01$
ChiPFormer ( Lai et al., 2023 )	$-322.05$	$-15426.07$	$-80.57$	$-378.90$
LaMPlace ( Geng et al., 2025 )	$-36.87$	$-1514.73$	$-66.93$	$-426.91$
PPAPlace zero-shot	$-68.50$	$-1380.50$	$-73.40$	$-440.50$

Table 5. Final timing on Superblue16/18, with baselines from LaMPlace ( Geng et al., 2025 ) . WNS is in

10^{3}

ps and TNS in

10^{5}

ps. Values closer to zero are better.

Label stage $\times$ representation
Training labels	Architecture	$\tau$ (WNS)	Top-1
Pre-route STA	Macro-only poly.	0.08 $\pm$ .02	n/a
Pre-route STA	GAT+CNN	0.13 $\pm$ .03	26%
Post-GRT	Macro-only poly.	0.18 $\pm$ .02	n/a
Post-GRT	GAT+CNN	0.31 $\pm$ .02	52%
Label stage (GAT+CNN fixed)

Table 6. Ablation on labels and representation (Kendall’s

\tau

, WNS). Upper: two label stages

\times

two representations. Lower: label stages with GAT+CNN fixed.

Macro Placement

See all 8 papers

Jul 19, 2026

CoEvoP&R: Co-Evolving Placement Objectives with Routing Feedback via Large Language Models

Analytical placers rely on differentiable objective functions to guide placement, typically combining intermediate surrogate metrics such as half-perimeter wirelength (HPWL) and cell-density penalties. However, these placement-stage surrogates remain misaligned with downstream routed and timing quality. Prior work reduces this gap with human-designed terms or learned black-box surrogates, but the former requires expert retuning and the latter is difficult to explain, debug, or deploy in analytical placement flows. CoEvoP&R addresses these limitations with a large language model (LLM)-based framework that automatically evolves analytical placement objectives. At each generation, the prompt combines the restricted objective interface, baseline context, and archived prior candidates with routing-related feedback from placement, timing proxy, and routing tools. The LLM proposes readable differentiable objectives, which are embedded and validated in DREAMPlace, evaluated through a timing proxy and an actual router, and stored with their feedback to guide later generations. Across eight ChiP-Bench Nangate45 designs and three seeds, CoEvoP&R reduces post-route routed wirelength and congestion by 16.9% and 36.7%, with gains of 0.70 ns in worst negative slack and a 912 ns reduction in total negative slack magnitude over native DREAMPlace. Across eight ICCAD 2015 Superblue designs, it reduces post-route routed wirelength and congestion by 5.4% and 23.2%. Code is available at https://github.com/FCHXWH823/CoEvoP-R.git.

Ruogu Chen, Weihua Xiao, Ramesh Karri +1

University of Alberta Edmonton, Alberta, Canada · New York University New York, New York, United States

Automated Heuristic Design Large Language Model-Guided Optimization Electronic Design Automation

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Apr 26, 2026

FlowPlace: Flow Matching for Chip Placement

Chip placement plays an important role in physical design. While generative models like diffusion models offer promising learning-based solutions, current methods have the following limitations: they use random synthetic data for pre-training, require long sampling times, and often result in overlaps due to their dependence on gradient-based solvers during the sampling process. To overcome these issues, we propose FlowPlace, which features mask-guided synthetic data generation, flow-based efficient training with flexible prior injection, and hard constraint sampling for overlap-free layouts. Experiments on OpenROAD and ICCAD 2015 benchmarks show FlowPlace achieves better PPA metrics, 10-50

\times

faster sampling efficiency, and zero overlaps.

Peng Xie, Ke Xue, Yunqi Shi +6

1State Key Laboratory of Novel Software Technology, Nanjing University, China · School of Artificial Intelligence, Nanjing University, China · 3Huawei Noah’s Ark Lab, China

Constrained Generative Modeling Flow Matching Electronic Design Automation Generative Modeling Flow-Based Generative Modeling

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Mar 30, 2026

See it to Place it: Evolving Macro Placements with Vision-Language Models

We propose using Vision-Language Models (VLMs) for macro placement in chip floorplanning, a complex optimization task that has recently shown promising advancements through machine learning methods. Because human designers rely heavily on spatial reasoning to arrange components on the chip canvas, we hypothesize that VLMs with strong spatial reasoning capabilities can effectively complement existing placement algorithms. We introduce VeoPlace (Visual Evolutionary Optimization Placement), a novel framework that uses a VLM, without any fine-tuning, to guide the actions of a base placer by constraining it to subregions of the chip canvas. The VLM proposals are iteratively optimized through an evolutionary search strategy with respect to resulting placement quality. Using global half-perimeter wirelength (gHPWL) after standard-cell placement and legalization as the evaluation metric, VeoPlace boosts ChiPFormer performance on 9 of 10 benchmarks with peak reductions exceeding 32%. We further demonstrate that VeoPlace generalizes to analytical placers, improving DREAMPlace on all 8 evaluated Superblue benchmarks with gains up to 4.4%. Our approach opens new possibilities for electronic design automation tools that leverage foundation models to solve complex physical design problems.

Ikechukwu Uchendu, Swati Goel, Karly Hou +5

Harvard University, Cambridge, MA, USA · Kempner Institute for the Study of Natural and Artificial Intelligence, Harvard University, Cambridge, MA, USA · Google DeepMind

Macro Placement Electronic Design Automation

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Abstract

Macro Placement

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