Hardware-in-the-Loop Phase-Aware CNN for Real-Time 5G Channel Estimation

Javad Zolfaghari-Bengar; Rakibul Rony; Elisa Gomez-de-Lope; Alejandro Villena-Rodriguez; Abhinav Mahadevan; Nicolas Kourtellis

eess.SPAug 11, 2026

Hardware-in-the-Loop Phase-Aware CNN for Real-Time 5G Channel Estimation

Authors: Javad Zolfaghari-Bengar, Rakibul Rony, Elisa Gomez-de-Lope, Alejandro Villena-Rodriguez, Abhinav Mahadevan, Nicolas Kourtellis

Organizations: Keysight AI Labs

Abstract

This demo presents real-time AI-based uplink channel-estimation inference using data collected from a hardware-in-the-loop 5G platform. The data-collection setup integrates commercial RF signal generation, programmable channel emulation, an O-RAN Radio Unit, DU emulation, and a lightweight phase-aware convolutional neural network (CNN) that estimates the channel response directly from received DMRS signals. Unlike simulation-only evaluations, the hardware-derived dataset exposes the estimator to practical RF and system-level impairments, including calibration mismatches, synchronization imperfections, quantization effects, phase noise, and implementation-specific nonlinearities. During the demo, attendees will observe real-time CNN inference and channel reconstruction using captured hardware-generated DMRS observations and compare the proposed CNN against Least Squares (LS) and frequency-domain LMMSE baselines. The objective is to showcase a practical AI-native physical-layer inference pipeline that combines hardware-derived 5G data with real-time neural channel estimation for future 5G-Advanced and 6G systems.

Figures & tables

Component	Description
RF generators	$2\times$ Keysight MXG N5182B
Channel emulator	Keysight PROPSIM F8800B
Radio Unit	Liteon O-RAN RU
DU emulator	Keysight S5040A
Training platform	Apple MacBook Pro (M4 Pro, 24 GB unified memory)
GPU acceleration	Apple integrated GPU using TensorFlow Metal

TABLE I: Hardware Data-Collection and AI Inference Platform

Parameter	Value
Wireless standard	5G NR uplink
Carrier frequency	$3.5$ GHz
Bandwidth	$100$ MHz
Numerology / SCS	$1$ / $30$ kHz
FFT size	$4096$
Resource blocks	$273$

TABLE II: 5G NR Uplink System Parameters

Fig. 2: AI processing pipeline used in the demonstration: previously captured hardware-derived DMRS observations are normalized by the transmitted DMRS, reshaped with sine–cosine phase encoding, and processed by the CNN in real time to produce the channel estimate.

Layer	Type	Filters	Kernel / Act.
Input	—	—	$[\,\cdot,\,N_{sc},\,U\!\times\!R,\,3\,]$
Layer 1	Conv2D + BN	$32$	$(5,1)$ / ReLU
Layer 2	Conv2D + BN	$64$	$(5,3)$ / ReLU
Layer 3	Conv2D + BN	$64$	$(3,3)$ / ReLU
Layer 4	Conv2D + BN	$32$	$(3,1)$ / ReLU
Layer 5	Conv2D	$3$	$(1,1)$ / Linear

TABLE III: CNN Architecture Used for Channel Estimation

Scenario	Model	Indoor/Outdoor	LOS/NLOS
RMa_indoor	RMa	Indoor	—
RMa_LOS	RMa	Outdoor	LOS
RMa_NLOS	RMa	Outdoor	NLOS
UMa_indoor	UMa	Indoor	—
UMa_LOS	UMa	Outdoor	LOS
UMa_NLOS	UMa	Outdoor	NLOS

TABLE IV: Channel Scenarios in the Demonstration Dataset

Fig. 3: Channel-estimation error versus SNR for LS, LMMSE, and the proposed phase-aware CNN on hardware-derived data.

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Wireless Communications Hardware-Software Co-Design Channel Estimation FPGA-Based Neural Network Acceleration

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Channel estimation is crucial in 5G communication networks for optimizing transmission parameters and ensuring reliable, high-speed communication. However, the use of multiple-input and multiple-output (MIMO) and millimeter-wave (mmWave) in 5G networks presents challenges in achieving accurate estimation under strict latency requirements on resource-limited hardware platforms. To address these challenges, we propose SwiftChannel, an algorithm-hardware co-design framework that integrates a hardware-friendly deep learning-based channel estimator with a dedicated accelerator. Our approach employs a convolutional neural network enhanced with a parameter-free attention mechanism, which effectively reconstructs full-resolution spatial-frequency domain channel matrices from low-resolution least squares (LS) estimates. We further develop a multi-stage model compression pipeline combining knowledge distillation, convolution re-parameterization, and quantization-aware training, resulting in substantial model size reduction with negligible accuracy loss. The hardware accelerator, implementing the compressed model and the LS estimator on FPGA platforms using High-level Synthesis (HLS), features a fine-grained pipeline architecture and optimized dataflow strategies. Tested on a Zynq UltraScale+ RFSoC, the accelerator achieves sub-millisecond latency, providing up to 24x speed-up and over 33x improvement in energy efficiency compared to GPU-based solutions. Extensive evaluations demonstrate that the proposed design generalizes not only across various noise levels and user mobilities, but also to a variety of unseen channel profiles, outperforming state-of-the-art baselines. By unifying algorithmic innovation with hardware-aware design, our work presents a future-proof channel estimation solution for 5G MIMO systems.

Abstract

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