GoalEvolve: From Handcrafted Algorithm Priors to Goal-Driven Evolution of Physical Design Algorithms
Organizations: Fudan University Shanghai, China
Abstract
Physical design algorithms operate within tightly coupled, multi-stage optimization flows, where stage-local gains may vanish or induce downstream degradation. Existing program-evolution frameworks often rely on stage-local objectives or undifferentiated multi-metric feedback, which neither guarantee better final results nor identify which unmet requirement should guide the next iteration. We present GoalEvolve, a goal-driven framework that makes physical design algorithm evolution accountable for the final quality of results (QoR) of the complete flow. Given a multi-objective QoR target region, GoalEvolve converts unmet requirements into normalized target gaps, identifies the dominant bottleneck, and uses stage-resolved checkpoint evidence to locate the responsible stage. An LLM-based Teacher then narrows the search to a relevant algorithmic decision and source region, while parallel Student agents implement and validate hypotheses through full-flow evaluation. Local effects, optimization debt, and downstream retention are retained as mechanism evidence for subsequent evolution. Across eight ASAP7 designs, GoalEvolve improves post-route TNS by 30.67% on average and reduces leakage and dynamic power by 21.18% and 9.42% versus default OpenROAD. Relative to commercial-tool goals, it closes 62.20% of the normalized power gap on power-dominant designs, surpasses the TNS goals on both timing-dominant designs, and closes 32.48% of the equal-weight timing-power gap on joint designs. Across all three designs evaluated against Codex goal mode under matched budgets, GoalEvolve further improves TNS by 26.46% while reducing leakage and dynamic power by 12.38% and 0.76%, respectively.
Figures & tables
| Design | (ns) | ( ) | ( ) | Runtime (s) | ||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| AES | / | / | 96.3 / | 35.0 / | 29.1 | 431,903.7 / | 350,000.0 / | 335,607.1 | 32 / | – / | 235 | |
| Ariane | / | / | 17,900.0 / | 17,600.0 / | 17,935.1 | 640,100.0 / | 623,000.0 / | 588,058.6 | 687 / | – / | 378 | |
| JPEG | / | / | 174.0 / | 80.0 / | 114.5 | 293,826.0 / | 250,000.0 / | 270,427.7 | 187 / | – / | 745 | |
| MemPool | / | / | 3,070.0 / | 1,210.0 / | 3,059.5 | 275,930.0 / | 185,000.0 / | 249,586.4 | 1,415 / | – / | 489 | |
| NVDLA-A | / | / | 321.0 / | 46.3 / | 285.3 | 164,679.0 / | 126,000.0 / | 144,228.6 | 166 / | – / | 828 | |
| NVDLA-C | / | / | 17,300.0 / | 16,500.0 / | 17,259.4 | 583,700.0 / | 583,000.0 / | 584,086.0 | 632 / | – / | 124 | |
| Design | Timing potential | Total-power potential | Profile |
|---|---|---|---|
| AES | +3.54% | +18.97% | Power-dominant |
| Ariane | +75.56% | +2.64% | Timing-dominant |
| JPEG | -8.67% | +14.94% | Power-dominant |
| MemPool | +49.73% | +33.26% | Joint |
| NVDLA-A | -44.66% | +23.61% | Power-dominant |
| NVDLA-C | +82.01% | +0.25% | Timing-dominant |
| Design | RB passes | (ns) GE/RB | ( W) GE/RB | (mW) GE/RB |
|---|---|---|---|---|
| AES | 7 | |||
| JPEG | 3 | |||
| NVDLA-A | 4 | |||
| NVDLA-M | 11 | |||
| NVDLA-P | 8 |
| Design | (%) | (%) | |
|---|---|---|---|
| Ariane | +91.10 | +7.86 | 0.373191/ 0.372333 |
| JPEG | +10.01 | +3.26 | 0.525724/ 0.277710 |
| MemPool | +22.60 | +11.06 | 0.732363/ 0.725688 |
| NVDLA-A | +64.75 | +0.80 | 0.637591/ 0.447106 |
| NVDLA-C | +86.16 | -0.05 | 0.817592 /0.833560 |
| NVDLA-M | +8.23 | +6.24 | 0.751243/ 0.581600 |
| Design | Valid rounds/evals. | (ns) | (mW) | ( W) |
|---|---|---|---|---|
| (GE; CGM) | GE / CGM | GE / CGM | GE / CGM | |
| Ariane | GE: r, evals. | |||
| CGM: evals. | ||||
| NVDLA-M | GE: r, evals. | |||
| CGM: evals. | ||||
| NVDLA-P | GE: r, evals. |
Electronic Design Automation
Electronic Design Automation uses algorithms and software to design, verify, optimize, and manufacture electronic circuits and systems.
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