Hybrid ML for Lightweight Pre-Route Delay Estimation in Open-Source IC Design

Marvin Castro Castro; Erick Carvajal Barboza

cs.LGAug 18, 2026

Hybrid ML for Lightweight Pre-Route Delay Estimation in Open-Source IC Design

Authors: Marvin Castro Castro, Erick Carvajal Barboza

Organizations: Universidad de Costa Rica

Abstract

Static Timing Analysis (STA) is a critical step in the design flow of digital integrated circuits, however, obtaining accurate delay estimations can represent a challenge when limited information regarding physical design is available. In response, this work presents a hybrid and light-weight machine learning (ML) based approach that combines a decision tree with linear regression to improve pre-routing delay estimations generated by the open-source RTL-to-GDSII tool OpenLane. The proposed model achieves an 80% reduction in error compared to OpenLane's estimates, demonstrates a 71% improvement even without utilizing OpenLane-specific parameters. Overall, this method offers an alternative to traditional delay propagation techniques and more complex machine learning models that is not only accurate, but is also over 300 times smaller, 2 times faster and offers a higher explainability.

Figures & tables

Data Scaling	Context Features	Distance Parameter	Tree Depth	.pkl Size (MB)	Variations		Unseen
Data Scaling	Context Features	Distance Parameter	Tree Depth	.pkl Size (MB)	RMSE	Correlation	RMSE	Correlation
Normalized	No	Yes	10	9.83	0.5977	0.93	0.8193	0.91
Normalized	Yes	Yes	5	12.94	0.5465	0.94	0.8489	0.90
No	No	Yes	13	9.83	0.5942	0.93	0.8212	0.91
OpenLane Pre-Route Estimation					2.503	0.428	1.199	0.704

TABLE I: Model Selection Results

	Hybrid Model w/ Delay		Hybrid Model wo/ Delay		OpenLane pre-route
Circuit	RMSE	Correlation	RMSE	Correlation	RMSE	Correlation
picorv32	0.879	0.901	1.276	0.775	1.216	0.696
zipdiv	0.859	0.899	1.238	0.777	1.057	0.807
s38417	0.663	0.924	0.973	0.824	2.730	0.413
s15850	0.656	0.922	0.947	0.826	0.629	0.333

TABLE II: Detailed Delay Prediction Results for the Hybrid Model and the Open Source Tool

	Pre-Route OpenLane	Estimations w/ Delay			Estimations wo/ Delay
	Pre-Route OpenLane	Full Estimation [ 4 ]	Delta Estimation [ 6 ]	Ours	Full Estimation [ 5 ]	Delta Estimation [ 6 ]	Ours
s15850	0.629	0.563	0.522	0.656	0.679	0.848	0.947
s38417	2.73	0.849	0.835	0.663	1.2176	0.550	0.973
picorv32	1.216	1.008	1.024	0.879	1.3001	1.076	1.276
zipdiv	1.057	1.052	1.031	0.859	1.3975	1.040	1.238

TABLE III: Detailed Delay Comparison Between the Hybrid Model and Other Models

Electronic Design Automation

Electronic Design Automation uses algorithms and software to design, verify, optimize, and manufacture electronic circuits and systems.

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Oct 5, 2026J/K move · Enter open · S save

Climbing the Design Ladder: Sequential Knowledge Distillation for Early-Stage Circuit Timing Prediction

Reza Moravej, Fahad Rahman Amik, Zhanguang Zhang, Didier Chételat+1

Huawei Noah’s Ark Lab · McGill University

Electronic Design Automation Knowledge Distillation

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Integrated circuit design involves multiple design stages: logic synthesis, floorplanning, placement, and routing, with each stage taking hours to weeks to complete. Discovering timing violations late in this flow forces costly iterations back to earlier stages, wasting computational resources and delaying product launches. While predicting post-routing timing from early-stage data could prevent these failures, existing machine learning approaches struggle with the massive abstraction gap between post-synthesis logical descriptions and post-routing physical layouts. We propose STEP-KD (Sequential Timing Evaluation via Progressive Knowledge Distillation), which leverages intermediate design stages as ``stepping stones'' for progressive knowledge transfer rather than attempting direct prediction. STEP-KD trains teacher models at the post-routing, post-placement, and post-floorplan stages, then sequentially distills their knowledge to a post-synthesis student model through representation alignment. Experiments on diverse circuits demonstrate that STEP-KD reduces timing prediction error compared to direct distillation and supervised baselines, and in most settings compared to the industry-standard Static Timing Analysis (STA) tool. STEP-KD reduces the weighted mean absolute percentage error of Total Negative Slack prediction to 19.78%, compared with 74.84% for STA. Our proposed method is step forward to identify timing problems earlier, avoiding expensive late-stage redesigns.

Abstract

Electronic Design Automation

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