We introduce Maia 200, an advanced AI accelerator delivering high performance-10 145 Tflop/s FP4 and 5072 Tflop/s FP8 within a 750W TDP and 7 TB/s HBM bandwidth. Maia exemplifies a new class of Software Defined Locally Accessed Dataflow Architectures (SDLA), which explicitly program dataflow engines to orchestrate highly specialized memories and data movement engines. This approach shifts the focus from today's thread-centric to data-movement-centric architecture, improving efficiency and scalability. Our taxonomy of data management, inspired by Flynn's classification, highlights how SDLA addresses challenges in modern AI computing. Maia 200 achieves significant cost and energy savings while supporting massive parallelism for AI inference workloads, making it a compelling solution for next-generation high-performance computing systems.
Figures & tables
Fig. 1: A Modern Data Management Classification of Processors Inspired by Flynn’s Original Instruction-focused Taxonomy from 1972.
Fig. 2: Abstract Machine Model for our Dataflow ISA.
Fig. 3: Maia 200 Abstract System on Chip Architecture. Processing blocks are shown in red, the data path is green with data movement accelerators in light green and memories in darker green, the NoC is in yellow, and the control path is in blue with synchronization engines in light blue and control processors in darker blue.
AI accelerator inference studies hardware and software for running neural networks faster and more efficiently across data-center, edge, and mobile devices.