PlaceReasoner-Beta: Reasoning-Driven Macro Placement and Benchmarking

Qiufeng Li; Chengxuan Wang; Rongqian Chen; Quan Cheng; Yihui Ren; Chia-Tung Ho; David Z. Pan; Tian Lan

Figure 1. A typical VLSI physical design workflow. Each stage shows its layout snapshot. Macro placement, the stage we target, fixes the large blocks (orange) and thereby the whitespace and channels left to stdcell placement (red) and CTS & routing (green). The inner blue arc refines a placement from geometric inspection alone and is cheap, whereas the outer one returns only after a full downstream run.

Figure 2. PlaceReasoner-Beta framework overview. It has four agents: Planner, Geometric Checker, Physical Checker, and Post-route Optimizer. These agents formulate three stages essential in physical design: (a) PlaceReasoner-Beta for macro placement generation and refinement, (b) detailed placement by getting early feedback, and (c) CTS & routing by getting final feedback.

Design	#Macros	#Clusters	#Types	Clk (ns)	M/Core (%)
ariane133	132	14	1	4.0	34.4
ariane81	81	8	6	4.0	36.0
bp_be	10	3	3	2.6	36.7
bp_fe	11	4	3	1.8	45.6
swerv_wrapper	28	3	3	2.0	44.1
vga_lcd	62	12	3	2.0	40.5

Table 1. Composition of PlaceReasoner-Bench. #Types counts distinct macro types, Clk is the target clock period, and M/Core is macro area as a fraction of core area. “–” denotes a quantity without aggregation.

Design	Method	Winner #	Route	WNS (ns)	TNS (ns)	DRC	WL ( $\mu$ m)	Power (W)	Area ( $\mu$ m 2 )	Runtime (s)	Token Usage (k)
ariane133	RTL-MP	2/5	Yes	-0.10	-4.60	0	5233982	0.265	729834	127.0	–
ariane133	DREAMPlace	3/5	Fail: timeout	–	–	–	–	–	–	11.00	–
ariane133	ChiPFormer	1/5	Yes	-0.04	-4.61	0	6211024	0.304	737387	16.96	–
ariane133	SA	–	Yes	-76.52	-579878	80223	7135797	0.286	718246	0.240	–
ariane133	CWI	1/5	Yes	-0.02	-0.52	0	6105080	0.266	733327	814.4	329.4
ariane133	CWS	5/5	Yes	-0.02	-0.56	0	5997840	0.265	732096	820.3	314.1

Table 2. Post-route results for four representative designs at the square (

1{:}1

) aspect ratio; the remaining four designs are reported in the appendix. “–” denotes an unavailable metric and failure states indicate that detailed routing did not complete. Winner # reports the one-based winner position

k/N

with

N=5

, and is undefined for the pure-model Qwen3-VL-8B and Qwen3-VL-30B rows, which report the single selected candidate. Runtime is macro-placement time for the classical baselines and summed model-driver time for the agent variants; Token Usage is the total of model input and output tokens. For ariane133, Qwen3-VL-30B left 18,166 residual violations, so its timing numbers are extracted from a non-converged routing and are not comparable with the clean rows.

Design	Method	Winner #	Route	WNS (ns)	TNS (ns)	DRC	WL ( $\mu$ m)	Power (W)	Area ( $\mu$ m 2 )	Runtime (s)	Token Usage (k)
ariane133	RTL-MP	1/5	Yes	-0.12	-25.29	0	6033112	0.276	731337	–	–
ariane133	DREAMPlace	–	Fail: timeout	–	–	–	–	–	–	–	–
ariane133	ChiPFormer	2/5	Yes	-0.39	-620	0	7079270	0.278	738872	–	–
ariane133	SA	–	Fail: GP1	–	–	–	–	–	–	–	–
ariane133	PlaceReasoner	4/5	Yes	-0.02	-0.08	0	5690597	0.285	730228	834.9	357.1
ariane133	Qwen3-VL-8B	–	Fail: GRT-0116	–	–	–	–	–	–	2228.3	479.9

Table 3. Post-route results for four representative designs at the elongated (

2{:}1

) aspect ratio; the remaining four designs are reported in the appendix. “–” denotes an unavailable metric and failure states indicate that detailed routing did not complete. Winner # reports the one-based position

k/N

of the selected candidate among the

N=5

trials of that run. Runtime and Token Usage are the summed model-driver time and the total of model input and output tokens, and are reported for the model-driven flows ( CWI , CWS , PlaceReasoner , and the two Qwen baselines); the non-LLM baselines incur no model cost.

Figure 3. Performance improvement of PlaceReasoner-Beta on post-route quality on the square (

1{:}1

) tasks: best- vs. worst-case improvement over the baselines, per design. Left: TNS; right: routed wirelength. For each design the best case (green) is the improvement over the weakest baseline and the worst case (orange) over the strongest; the shaded band spans the two. Improvement is

(\lvert x_{\text{base}}\rvert-\lvert x_{\textsc{pr}}\rvert)/\max(\lvert x_{\text{base}}\rvert,\lvert x_{\textsc{pr}}\rvert)

. That is,

+100\%

means PlaceReasoner-Beta drives the metric to zero and positive values (green zone) mean it is better. Although PlaceReasoner-Beta never optimizes wirelength, it still shortens it over the baselines on most designs.

Figure 4. Macro placements produced by different methods on bp_be at aspect ratio

1{:}1

, each annotated with the post-route TNS and DRC count it leads to; (j) is the routed layout obtained from the placement in (i). (a) SA and (c) DREAMPlace spread macros over the core interior and leave narrow, irregular gaps between them and the die boundary; the router cannot absorb the standard cells there, yielding

37{,}695

and

63{,}393

violations (in (c), red marks the congested region). (b) ChiPFormer and (d) RTL-MP route DRC-clean, but their interior macro columns cut the standard-cell area into disconnected strips, and timing stalls at

-54

and

-23.54

ns. (i) PlaceReasoner-Beta instead pushes every macro against the periphery in a single contiguous column, preserving one large standard-cell region and clear routing channels, and reaches

-9.42

ns with zero violations. The same effect is visible across backbones: (f) Qwen3-VL-30B also drives the macros to the periphery and reaches

-13.28

ns, whereas (e) Qwen3-VL-8B leaves them fragmented in the interior and stalls at

-28.59

ns. Panels (g) and (h) are the CWS and CWI ablations, discussed in the ablation study.

Figure 5. Macro placements on ariane133 at aspect ratio

2{:}1

, annotated with the post-route TNS and DRC count each leads to; (j) is the routed layout of (i), and “failed” marks runs whose detailed routing did not complete. The elongated core is unforgiving: five of the nine placements never route. (a), (c) and (f) leave the macros in a dense interior cluster (in (c), red marks the congested region), while (b) and (e) fragment the standard-cell area into disconnected strips; only ChiPFormer routes, at

-620

ns. (d) RTL-MP is the strongest baseline, holding an L-shaped ring along the left and bottom edges and reaching

-25.29

ns DRC-clean. (i) PlaceReasoner-Beta instead packs the macros into two bands against the short peripheries, leaving one uninterrupted standard-cell region across the die, and reaches

-0.08

ns with zero violations. Panels (g) and (h) are the CWS and CWI ablations, discussed in the ablation study.

Figure 6. Post-route improvement of PlaceReasoner-Beta on the elongated (

2{:}1

) tasks: best- vs. worst-case improvement over the four classical baselines, per design. Left: TNS; right: routed wirelength. For each design, the best case (green) is the improvement over the weakest baseline and the worst case (orange) over the strongest; the shaded band spans the two. Improvement is

(\lvert x_{\text{base}}\rvert-\lvert x_{\textsc{pr}}\rvert)/\max(\lvert x_{\text{base}}\rvert,\lvert x_{\textsc{pr}}\rvert)

, so

+100\%

means the metric is driven to zero and positive values (green zone) mean PlaceReasoner-Beta is better. A baseline that fails to route, or routes with more than

10{,}000

DRC violations, counts as a failed run: for TNS it scores a full

+100\%

win, which is why the best-case curve saturates; for wirelength it is excluded instead, and swerv_wrapper therefore drops from that panel because no baseline survives. Hollow markers on bp_fe and vga_lcd mark the two designs where the strongest baseline attains marginally better TNS but with more DRC violations than our run. Timing therefore improves on six of the eight designs, with a mean worst-case gain of

+44.3\%

, while routed wirelength is on par with the strongest baseline.

Metric	mean CV%	median CV%	max CV%	mean range%
TNS (ns)	80.36	72.83	190.36	170.35
WNS (ns)	43.72	19.36	152.96	89.83
Power (W)	1.56	1.16	5.28	3.18
Area ( $\mu$ m 2 )	0.27	0.19	0.98	0.56

Table 4. Which post-route metrics macro placement actually moves, aggregated over the 16 benchmark cells of Table 5 . “range%” is the candidate spread

(\max-\min)/|\mathrm{mean}|

. Timing varies by tens of percent between candidates of the same design, whereas power and area vary by at most a few percent.

Design	AR	Candidates		WNS (ns)		TNS (ns)		Power (mW)		Area ( $10^{3}\mu$ m 2 )
Design	AR	routed	clean	mean $\pm$ std	CV%	mean $\pm$ std	CV%	mean $\pm$ std	CV%	mean $\pm$ std	CV%
ariane133	$1{:}1$	2/5	1/2	$-0.190\pm 0.240$	126.5	$-234.0\pm 330.4$	141.2	$268.0\pm 14.1$	5.3	$732.5\pm 5.2$	0.71
ariane81	$1{:}1$	5/5	5/5	$-0.066\pm 0.019$	29.5	$-12.7\pm 13.4$	105.5	$195.2\pm 1.5$	0.8	$693.5\pm 1.2$	0.17
bp_be	$1{:}1$	5/5	5/5	$-0.226\pm 0.077$	34.1	$-19.3\pm 6.5$	33.7	$120.6\pm 2.1$	1.7	$239.2\pm 0.8$	0.34
bp_fe	$1{:}1$	3/5	3/3	$-0.257\pm 0.393$	153.0	$-15.9\pm 27.2$	171.5	$144.0\pm 5.2$	3.6	$215.1\pm 2.1$	0.98
swerv_wrapper	$1{:}1$	5/5	1/5	$-0.522\pm 0.070$	13.4	$-480.6\pm 56.3$	11.7	$244.4\pm 4.8$	2.0	$648.5\pm 1.7$	0.26

Table 5. Run-to-run PPA variance of PlaceReasoner on PlaceReasoner-Bench. Statistics are taken over the

N=5

placement candidates the planner generates for each design, using only those that complete detailed routing; “routed” counts them and “clean” how many of those are DRC-clean.

\mathrm{CV}\%=100\,\mathrm{std}/|\mathrm{mean}|

. Timing spreads widely across candidates while power and area stay within a few percent, which is why candidate selection is part of the workflow.

Figure 7. PPA of the five structurally distinct macro placements PlaceReasoner-Beta explores for bp_be at aspect ratio

1{:}1

, against RTL-MP (dashed), the strongest classical baseline on this design; the dark bar is the candidate the workflow selects. Timing is plotted as a magnitude, so lower is better in every panel. The candidates differ by a factor of

2.9

in TNS but by under

1\%

in area and

4.2\%

in power, and all five are DRC-clean. Every candidate is at least as good as RTL-MP in area and power, and four of five are better in TNS and WNS, so the advantage does not depend on which candidate is selected.

Figure 8. Macro placements of bp_fe at aspect ratio

2{:}1

, with each macro’s pin side marked by the dark bar on its edge; green and red bands are the I/O pins on the die boundary, and (j) is the routed layout of (i). Only (i) PlaceReasoner-Beta turns every pin side toward the standard-cell region: it mirrors the orientation of the two macro groups so that the left group faces right and the right group faces left, both onto the central corridor. (a) SA orients macros inconsistently across a scattered interior placement (

20{,}479

violations); (b) ChiPFormer packs one abutting block with uniformly oriented columns, so the left column faces the die boundary and the right column faces the back of the left, and it leaves

5

violations; (d) RTL-MP orients its main column inward but leaves the top-right macro facing the boundary beside a large dead region; (c) DREAMPlace does not complete routing. (e)–(f) Qwen3-VL-8B and Qwen3-VL-30B , and (g)–(h) the two ablations, apply a single orientation to every macro, so their left-hand macros face outward.

Figure 9. Macro placements produced by PlaceReasoner-Beta on the remaining 15 PlaceReasoner-Bench tasks, with each macro’s pin side marked: (a)–(h) the eight designs at aspect ratio

1{:}1

and (i)–(o) seven of them at

2{:}1

; bp_fe at

2{:}1

is the case of Fig. 8 and is not repeated here. Across designs and aspect ratios, the macros are grouped against the periphery and each group is oriented so that its pin side faces the standard-cell region it serves, leaving that region contiguous.

Figure 10. Optimization trajectory of the post-route optimizer on four designs at both aspect ratios. Each curve follows the incumbent placement, i.e. the candidate the workflow would ship after

k

rounds, normalized by the base plan at iteration

0

; values below

1

are improvements and both metrics are plotted as magnitudes. Color denotes the aspect ratio and line style the metric: solid with filled circles is WNS, dashed with open squares is TNS. A round that loses on timing or violates the DRC gate leaves the incumbent unchanged, which is why the curves are flat in places. The optimizer improves six of the eight runs, is unable to beat its base plan on bp_be and swerv_wrapper at

2{:}1

, and on vga_lcd at

2{:}1

improves WNS while degrading TNS.

Design	Method	Winner #	Route	WNS (ns)	TNS (ns)	DRC	WL ( $\mu$ m)	Power (W)	Area ( $\mu$ m 2 )	Runtime (s)	Token Usage (k)
ariane133	RTL-MP	2/5	Yes	-0.10	-4.60	0	5233982	0.265	729834	127.0	–
ariane133	DREAMPlace	3/5	Fail: timeout	–	–	–	–	–	–	11.00	–
ariane133	ChiPFormer	1/5	Yes	-0.04	-4.61	0	6211024	0.304	737387	16.96	–
ariane133	SA	–	Yes	-76.52	-579878	80223	7135797	0.286	718246	0.240	–
ariane133	CWI	1/5	Yes	-0.02	-0.52	0	6105080	0.266	733327	814.4	329.4
ariane133	CWS	5/5	Yes	-0.02	-0.56	0	5997840	0.265	732096	820.3	314.1

Table 6. Detailed post-route results for the square (

1{:}1

) tasks. “–” denotes an unavailable metric; failure states indicate that detailed routing did not complete. Winner # reports the one-based winner position

k/N

; use

N=5

; Runtime reports macro-placement time for the classical baselines, summed model-driver time for the agent variants. Token Usage is the total number of model tokens.

Design	Method	Winner #	Route	WNS (ns)	TNS (ns)	DRC	WL ( $\mu$ m)	Power (W)	Area ( $\mu$ m 2 )	Runtime (s)	Token Usage (k)
ariane133	RTL-MP	1/5	Yes	-0.12	-25.29	0	6033112	0.276	731337	–	–
ariane133	DREAMPlace	–	Fail: timeout	–	–	–	–	–	–	–	–
ariane133	ChiPFormer	2/5	Yes	-0.39	-620	0	7079270	0.278	738872	–	–
ariane133	SA	–	Fail: GP1	–	–	–	–	–	–	–	–
ariane133	CWI	–	Fail: GRT-0116	–	–	–	–	–	–	820.5	344.9
ariane133	CWS	1/5	Yes	-1.99	-2650.22	0	–	0.283	746548	827.6	348.7

Table 7. Detailed post-route results for the elongated (

2{:}1

) tasks. Use the same settings with square (1 : 1) tasks.

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