Automatic synthesis of analog and Radio Frequency (RF) circuits is an emerging area that requires an efficient circuit modeling method. In recent years, Machine Learning (ML) solutions have played a promising role in this regard. However, many existing ML approaches require separate training data for each circuit topology, even when a single circuit component is added or removed. In addition, they overlook circuit topology information, which limits their ability to capture complex component interactions. Furthermore, they rely on fully connected neural networks with flat feature representations, which require substantial amounts of training data. In this work, we propose an open-source topology-aware RF circuit modeling method, TARGet. Our model considers the circuit at two levels: sub-circuits and the overall circuit topology. At the sub-circuit level, TARGet leverages S-parameter representations to capture sub-circuit behavior rather than relying on individual circuit components, providing a reusable behavioral abstraction for RF building blocks. Moreover, TARGet explicitly incorporates circuit topology information into the model, enabling it to learn across multiple topologies. TARGet introduces a novel fusion-based architecture that integrates Graph Neural Networks (GNNs) and sub-circuit connectivity-aware neural networks to improve data efficiency. Experimental evaluation across multiple RF circuit topologies demonstrates that TARGet achieves sub-1% prediction error while reducing the required training data by up to 35.5x compared to state-of-the-art (SOTA) approaches. Furthermore, TARGet achieves 9.7x higher prediction accuracy under a strict 1% error threshold relative to SOTA models. A held-out matching-network evaluation further demonstrates zero-shot transfer to an unseen sub-circuit topology, where TARGet reduces NMAE by up to 45%.
Figures & tables
Figure 1. Overall TARGet framework. Block diagram of TARGet. A circuit is divided into sub-circuits and auxiliary components. S-parameter features are processed by a sub-circuit encoder branch, while a graph representation of nodes and edges is processed by a high-level topology encoder branch. The two embeddings, together with auxiliary features, are concatenated in a fusion block and passed through fully connected layers to predict circuit specifications.
Figure 2. An example of a circuit to graph decomposition in TARGet. (a) An RF circuit. (b) The corresponding graph. Two-panel example showing an RF circuit schematic on the left and its graph representation on the right. Dashed boxes mark sub-circuits in the schematic. The graph uses different node colors for sub-circuits, additional circuit components, and voltage sources, with edges representing electrical connections.
Spec
Min
Max
Average
SD
Input return loss [dB]
-116.94
0
-7.24
7.84
Insertion loss [dB]
-153.5
0
-5.46
8.9
Output return loss [dB]
-116.94
0
-7.24
7.84
Table 1. Statistics of phase-shifter database.
Spec
Min
Max
Average
SD
Power gain (GP) [dB]
-226.7
51.95
-12.08
16.68
Available gain (GA) [dB]
-226.7
11.25
-7.33
13.98
Noise Figure (NF) [dB]
2.41
3082.55
19.11
22.15
Table 2. Statistics of LNA database.
NN Model
Module
Configuration
FCNN
Hidden layers
FC [128, 256, 128]
CCI-NN
Sub-ANNs
FC branches [128, 128, 128]
Aggregation
FC [512]
GNN
Graph encoder
GCN layers [64, 64, 64]
Pooling
Global Avg Pool
Output head
FC [64, 32]
Table 3. Architectural details of TARGet and baseline models
Model
Input
Sub-circuit
Topology
Fusion
FCNN
Flat
–
–
–
CCI-NN
Grouped
✓
–
–
GNN
Graph
–
✓
–
TARGet
Hybrid
✓
✓
Late fusion
Table 4. Architectural comparison of TARGet and baseline models
Figure 3. Supported high-level topologies and sub-circuits. (a) LNA high-level topologies. (b) LNA sub-circuits. (c) Phase shifter high-level topology. (d) Phase shifter sub-circuits. For the zero-shot evaluation, one LNA sub-circuit topology is reserved as a held-out structure for zero-shot testing (red borders). Four-panel overview of the evaluated circuit families. The first panel shows common-source and cascode LNA high-level topologies with input and output matching blocks. The second panel shows the LNA matching-network sub-circuit library, with the held-out zero-shot topology marked by a red border. The third panel shows the high-level phase-shifter topology, and the fourth panel shows the phase-shifter sub-circuit library.
Figure 4. Model performance error (NMAE) for the LNA architecture across different specifications. (a,c,e) NMAE vs. training data utilization for GA, GP, and NF, respectively. (b,d,f) NMAE vs. frequency for GA, GP, and NF, respectively. Six line plots comparing TARGet with GNN, FCNN, and CCI-NN on the LNA dataset. The top row plots NMAE against training utilization for GA, GP, and NF, with arrows indicating large data reduction factors. The bottom row plots NMAE against frequency for the same specifications. In all panels, the TARGet curve stays below the baseline curves.
Spec
Metric
FCNN
CCI-NN
GNN
TARGet
GA
MAE
0.3417
0.3176
0.5019
0.0132
RMSE
0.4968
0.4655
0.6682
0.0198
NMAE
0.0784
0.0730
0.1145
0.0030
GP
MAE
0.2206
0.2015
0.2354
0.0126
RMSE
0.2429
0.2131
0.2510
0.0240
NMAE
0.0414
0.0378
0.0442
0.0024
Table 5. Performance comparison on the LNA architecture (lower is better).
Model
≤ 0.01
≤ 0.02
≤ 0.05
≤ 0.10
FCNN ( Fukuda et al., 2017 )
0.0987
0.1988
0.4901
0.7664
CCI-NN ( Hassanpourghadi et al., 2021 )
0.0940
0.1978
0.5350
0.7997
GNN ( Zhang et al., 2019 )
0.0526
0.1075
0.2997
0.5984
TARGet
0.9582
0.9936
0.9998
1.0000
Table 6. Tolerance-based evaluation for the LNA architecture (higher is better).
Figure 5. Comparison of predicted and ground-truth gain (GA) across frequency for the LNA architecture at full training data utilization. (a) Representative sample-level predictions. (b) Average GA across all samples, showing close agreement between model predictions and ground truth. Two plots of available gain versus frequency. The top plot compares real and predicted GA curves for a representative sample using TARGet, GNN, FCNN, and CCI-NN. The bottom plot compares the average GA over all samples. TARGet closely follows the real curve, especially in the averaged response.
Model
GA
GP
NF
FCNN
0.0856
0.0604
0.0649
CCI-NN
0.0833
0.0593
0.0671
GNN
0.1185
0.0656
0.0837
TARGet
0.0457
0.0482
0.0499
Table 7. Zero-shot transfer NMAE results on the held-out LNA topology using 10 uniformly selected frequencies at 100% utilization (lower is better).
Figure 6. Tolerance curves for the LNA architecture at full training data utilization. The curves show the fraction of predictions whose normalized error falls below a given threshold. Cumulative tolerance plot with NMAE tolerance threshold on the horizontal axis and fraction of samples within the threshold on the vertical axis. TARGet rises sharply and reaches nearly all samples at a low threshold, while FCNN, CCI-NN, and GNN increase more gradually.
Figure 7. Model performance error (NMAE) for the phase-shifter architecture for the input return loss specification. (a) NMAE as a function of training data utilization, illustrating model performance under data-scarce conditions. (b) NMAE across frequency, showing prediction consistency over the operating range. Two line plots for the phase-shifter dataset. The left plot shows NMAE versus training utilization, where all methods improve as utilization increases and TARGet, FCNN, and CCI-NN are close at high utilization. The right plot shows NMAE versus frequency, where GNN has higher error and the other three methods remain lower and close to each other.
Accurately predicting the performance of active radio frequency (RF) circuits is essential for modern wireless systems but remains challenging due to highly nonlinear behavior and the high computational cost of traditional simulation tools. Existing machine learning (ML) surrogates often require large datasets to generalize across various topologies or are not accurate on held-out circuits. This work presents a lightweight, data-efficient, and topology-aware graph neural network (GNN) framework for predicting key performance metrics of active RF circuit classes, such as low-noise amplifiers (LNAs), mixers, voltage-controlled oscillators (VCOs), power amplifiers (PAs), and voltage amplifiers (VAs). The proposed framework employs RFIC domain-informed feature indexing to enable cross-topology adaptability by cheap encoding of functional device semantics (e.g., differential pair and varactor transistors) and efficient knowledge transfer. The surrogate model represents circuits using device-terminal graph abstractions to preserve fine-grained connectivity and transistor-level symmetry. The final model is generalized to a wide variety of classes by being trained in parallel. Experimental results demonstrate accurate modeling of multimodal and heavy-tailed RF performance distributions, achieving an average mean relative error (MRE) of 2.71% across nineteen topologies, an improvement of 3.3x and 20x faster in training over prior art, and the generalization to held-out topologies is improved by ~26.2x. Furthermore, this work shows ~36x training data efficiency compared to state-of-the-art, demonstrating its effectiveness for scalable and deployment-ready RF design automation.
Anahita Asadi, Leonid Popryho, Inna Partin-Vaisband
Department of Electrical and Computer Engineering, University of Illinois Chicago, Chicago, IL 60607 USA
Analog/RF circuits remain the critical interface between digital computation and the physical world, and emerging standards from Wi-Fi 7 to 6G place stringent demands on them, yet analog/RF design remains one of the most labor-intensive steps in chip development. We present RFChipAgent, a first-of-its-kind multi-agent flow of large language model (LLM) agents for end-to-end analog/RF circuit design automation, in which AI agents collaboratively orchestrate the complete design flow under human supervision. RFChipAgent is built around four technical pillars. First, a multimodal retrieval-augmented generation (RAG) subsystem with private per-document FAISS indexing extracts design knowledge from existing engineering documentation. Second, a topology agent drives topology selection, and a schematic and testbench agent automates circuit and testbench assembly. Third, a closed-loop hybrid circuit-sizing engine combines Tree-structured Parzen Estimator (TPE) and CMA-ES optimization, evaluating every candidate in a simulator-in-the-loop framework. Fourth, a trust-scored simulation database accumulates verified performance data and builds an adaptive optimization model that informs subsequent trials. We validate RFChipAgent on a family of GF22FDSOI 60 GHz wideband mm-wave low-noise amplifier (LNA) topologies, demonstrating automated topology generation, specification-driven design-space exploration, and simulator-guided optimization. Experimental results show substantial reductions in design effort while maintaining signoff-quality verification. This work establishes a foundation for LLM-driven multi-agent electronic design automation (EDA) for analog/RF circuits.
Large language models (LLMs) have driven rapid progress in electronic design automation (EDA), yet their application to radio-frequency (RF) circuit design remains limited by the scarcity of domain-specific datasets and standardized benchmarks. We present RF-Agent, which addresses this gap through textbook-driven knowledge distillation. A multi-agent Question-Thinking-Solution-Answer (QTSA) pipeline converts a subsection-level corpus from seven canonical RF textbooks into the first-of-its-kind RF-domain reasoning dataset (over 11,000 samples) with a dedicated multiple-choice benchmark. On this benchmark we study two adaptation strategies: supervised fine-tuning (SFT) and three retrieval-augmented generation (RAG) configurations (semantic, keyword, hybrid). Across multiple LLM families, domain-specific SFT significantly improves RF reasoning, especially for small and medium-sized models; among RAG configurations, semantic retrieval performs best, indicating embedding-based context alignment suits RF reasoning better than naive fusion. The dataset and benchmark provide a reusable foundation for future work on LLM-aided RF circuit design.
Yueqi Xing, Houbo He, Jolie Wang +5
ECE Department, Rice University, Houston, TX, USA · ECE Department, The George Washington University, Washington, D.C., USA