Analog Circuit Sizing

Follow this topic Ask about this topic

Latest papers

13 papers5 papers in the last four weeks, against 1 the four weeks before. 0.0% of all new papers.

LOADBench: A Large Open Analog Dataset and Benchmark for Machine Learning in IC Design
Oct 15, 2026M. Leibl, F. Azevedo, S. Uhlich +7Electronic Design Automation Benchmark Design
TUM / Chair of Electronic Design Automation · Instituto de Telecomunicações (IT) / IST-UL · SonyAI +4
CktHGVAE: A Symmetric Design/State Heterogeneous Graph Variational Autoencoder for Transistor-level Analog/Mixed-signal Circuit Design and Analysis
Oct 14, 2026Shigeyasu UnoAnalog Circuit Sizing Electronic Design Automation
Ritsumeikan University, 1-1-1 Noji-Higashi, Kusatsu, Shiga 525-8577, Japan
RFChipAgent: Multi-Agentic AI Flow for Analog/RF Chip Design
Oct 7, 2026Awani Khodkumbhe, Yunfei Feng, Raj Rangarajan +2Electronic Design Automation Analog Circuit Sizing
Qualcomm Technologies, Inc. · UC Berkeley
SGAnalog: An End-to-End Circuit Benchmark from Open-Source Silicon Tapeouts
Oct 2, 2026Yueting Li, Weihang DingElectronic Design Automation Benchmark Design
University of California, Berkeley
AgenticSizing: A Large Language Model-based Multi-Agent Framework for Analog Circuit Sizing
Sep 22, 2026Yijia Hao, Pratibha Verma, Dongxu Guo +4Large Language Model-Guided Optimization Electronic Design Automation
Centre for Electronics Frontiers, Institute for Integrated Micro and Nano Systems, School of Engineering, The University of Edinburgh, UK · Department of Electrical Engineering, Indian Institute of Technology Indore, India · School of Informatics, The University of Edinburgh, UK +1
Analog-DB: An Agent-First Analog Integrated Circuit Database, From Blocks to Systems
Sep 1, 2026Danial Noori Zadeh, Mohamed B. ElamienCircuit Discovery Electronic Design Automation
The authors are with the Department of Electrical and Computer Engineering, McMaster University, Hamilton, ON, Canada
AaLLM: An End-to-End Analog Circuit Design Framework from Topology Generation to Sizing Using Large Language Models
Aug 13, 2026Mohammed Ayman Habib, Rylan Hart, Morteza FayaziMulti-Agent LLM Systems Electronic Design Automation
University of Utah, Salt Lake City, Utah, USA
SPECS: Speciated Evolutionary Circuit Synthesis
Jul 15, 2026Yağız Gençer, Stefan Uhlich, Andrea Bonetti +3Topology Optimization Electronic Design Automation
Sony Group Corporation, Switzerland · TU Munich, Germany
Lighthouse RL: Sample-Efficient Circuit Optimization via Strategic Reset Points
Jul 15, 2026Mustafa Emre Gürsoy, Stefan Uhlich, Ryoga Matsuo +6Reinforcement Learning Black-Box Optimization
1Sony Group Corporation, Switzerland · 2EPFL, Switzerland · 3Sony Semiconductor Solutions, Japan +1
PANDA: An LLM-Enhanced Performance-Driven Analog Design Framework Bridging Design Intent and Layout Generation
Jun 13, 2026Haoyi Zhang, Weijian Fan, Xiaohan Gao +3Large Language Model-Guided Optimization Electronic Design Automation
School of Integrated Circuits, Peking University, Beijing, China · Beijing Advanced Innovation Center for Integrated Circuits, Beijing, China · Institute of Electronic Design Automation, Peking University, Wuxi, China
A Self-Calibrating Framework for Analog Circuit Sizing Using LLM-Derived Analytical Equations
Apr 8, 2026Antonio J. Bujana, Aydin I. KarsilayanElectronic Design Automation Analog Circuit Sizing
Department of Electrical and Computer Engineering, Texas A&M University, College Station, TX, USA. · Department of Engineering, Benedictine College, Atchison, KS, USA.
Can an Actor-Critic Optimization Framework Improve Analog Design?
Mar 25, 2026Sounak Dutta, Fin Amin, Sushil Panda +3Analog Circuit Sizing Electronic Design Automation
North Carolina State University, Department of Electrical and Computer Engineering, Raleigh, North Carolina, USA
VLM-CAD: VLM-Optimized Collaborative Agent Design Workflow for Analog Circuit Sizing
Jan 12, 2026Guanyuan Pan, Shuai Wang, Yugui Lin +4Bayesian Optimization Electronic Design Automation
Hangzhou Dianzi University, China · SCBC, Guangdong University of Foreign Studies, China · University of Cambridge, United Kingdom

Oct 15, 2026J/K move · Enter open · S save

LOADBench: A Large Open Analog Dataset and Benchmark for Machine Learning in IC Design

M. Leibl, F. Azevedo, S. Uhlich, A. Bonetti+6

TUM / Chair of Electronic Design Automation · Instituto de Telecomunicações (IT) / IST-UL · SonyAI+4

Electronic Design Automation Benchmark Design Analog Circuit Sizing Multi-Objective Optimization

Open paper AskPDF arXiv

Machine learning (ML) for analog IC design is constrained by limited open data and the absence of standardized evaluation: results reported in different papers are typically obtained on bespoke, often closed, datasets and with ad-hoc metrics, leaving comparisons across methods unreliable. We address both gaps with a large opensource dataset and a suite of standardized benchmarks. The dataset contains more than 100 operational amplifier (opamp) topologies (1-, 2-, and 3-stage) in the SkyWater130 PDK, each shipped with structural and functional annotations, topology-specific sizing constraints (symmetry and sizing rules), an Ngspice testbench, and a multi-objective NSGA-II sizing run producing around 103 Pareto-optimal and 106 intermediate sizing-performance pairs per topology. On top of this data we define six benchmark tasks with precise protocols: inverse sizing, topology selection, sub-circuit classification, structural circuit generation, Pareto-membership prediction, and multi-objective optimization. Thus, the data presented here constitutes the most comprehensive dataset for ML development in over four decades of analog IC design automation. The dataset, ground-truth annotations, and reference implementations of the metric-defining routines are released under an open license, enabling reproducible and directly comparable evaluation across heterogeneous analog design automation methods.