GLASS: Architecture-Tuned, Composable, Device-Side Linear Algebra for Edge Robotics and Beyond

Brian Plancher

cs.ROSep 23, 2026

GLASS: Architecture-Tuned, Composable, Device-Side Linear Algebra for Edge Robotics and Beyond

Authors: Brian Plancher

Organizations: Dartmouth College

Abstract

GPU robotics lacks the reusable numerical infrastructure of mature CPU stacks, instead relying on compiler frameworks that introduce overhead or repeatedly reimplementing numerical libraries. To address this, we introduce GLASS (GPU Linear Algebra Simple Subroutines), a header-only CUDA C++ library that provides thread-, warp-, block-, and NVIDIA-backed implementations of robotics-scale linear algebra and geometric computations under one composable device API. GLASS treats implementation choice, execution scope, and launch packing as architecture-specific placement decisions determined by offline measurement and resolved statically at compile time. This is critical as the best and worst placements differ by a median of 4.9x (max 81x), with 145 of 396 recommended placements changing between a Jetson AGX Orin and an RTX 5090, and 162 of 396 versus an AGX Xavier. These stakes are highest at the edge as GLASS's advantage over the best of PyTorch and JAX is as much as 73x on the Orin versus 12x on the RTX 5090. GLASS is released open source with independent numerical oracles and source-bound local-GPU test attestation. Finally, integrating GLASS with published robotics systems both exposed a pre-existing numerical bug and improved embedded runtimes by up to 1.5x.

Figures & tables

		LA + Fact.	Robotics	Guided
Library	Scope	+ Solves	+ fused	selection
JAX, PyTorch	host $\to$ batch	✓	—	(✓)
cuBLAS/cuSOLVER	host $\to$ batch	✓	—	—
MAGMA, KBLAS	host $\to$ batch	✓	—	(✓)
cuBLASDx/cuSOLVERDx	thread/block	✓	—	—
CUB, CUTLASS	thread/warp/block	(✓)	—	(✓)

TABLE I: Representative GPU numerical libraries and the capabilities. Parentheses denote partial support (e.g., a subset of functions, profiler- or heuristic-guided choices).

Panel of Figure 2 — Fig. 1: GLASS at a glance. Application kernels call one device-side API spanning thread-, warp-, block-, and NVIDIA-backed implementations. Offline measurement produces architecture-specific compile-time dispatch and launch placements. Independent numerical tests validate every implementation separately from performance measurement.

Fig. 2: Measured fp32 kernel timings on the Jetson AGX Orin at

B=8192

. Each panel reports per-problem time as problem size varies. Native GLASS Thread, Warp, and Block implementations are measured alongside NVIDIA device paths where supported. Sampled problem sizes are spaced uniformly to expose the small-

N

regime. Crossings show why no single execution scope provides the best implementation and why placement matters.

Fig. 3: Other device-side comparisons over limited matched supported operations on the Jetson AGX Orin, confirming GLASS’s advantage due to its broader set of execution placements and numerical primitives.

Fig. 4: Recommended fp32 placements across operation, problem size, and batch size on the RTX 5090, Jetson AGX Orin, and Jetson AGX Xavier. Colors denote native Thread, Warp, and Block execution and NVIDIA-backed implementations. Black outlines mark recommendations that differ from the Orin’s (center row, shaded). For the Xavier much of this divergence is structural as it cannot support the evaluated NVIDIA device libraries.

Fig. 5: Penalty from transferring native placements and launch configurations between GPU architectures across the 396 measured cells. Rows are source hardware and columns are target hardware. Each off-diagonal entry reports geometric-mean and 95th-percentile slowdown relative to the locally tuned target plan. One Orin placement (16 warp-packed fp64 GEMM problems per block) exceeds the RTX 5090’s per-block shared memory and cannot be transferred.

Fig. 6: Host-batched baseline time divided by the best measured valid native GLASS time for fp32 GEMM, POTRF, and POSV on the Jetson AGX Orin against cuBLAS/cuSOLVER (top) and the per-cell best of PyTorch and JAX batched linear algebra with device-resident inputs and outputs and pre-compiled and jitted code (bottom). Values above one favor GLASS and are clipped to 16 $\times$ for visual clarity (true maximum value is 113.9 $\times$ ), exposing both the small-matrix region where device-side execution wins and the larger regimes where host batching can regain some advantage, and exposing the benefit of a flexible, portable, and adaptable placement framework.

Operation	Block	Warp	Thread	Block/best
quat_retract	10.291	5.752	2.869	$3.6\times$
se3_retract	14.768	9.930	4.152	$3.6\times$
quat_error	8.589	4.819	2.330	$3.7\times$
motion_cross_mul	12.092	7.322	3.417	$3.5\times$
eig3	62.519	46.891	8.012	$7.8\times$
svd3	77.071	56.280	11.831	$6.5\times$

TABLE II: Execution placement for representative robotics operations. ns/problem for fp32 on the Jetson AGX Orin at

B=4{,}096

Fig. 7: Runtime ratio of the unfused GLASS Riccati composition (one kernel per primitive, intermediates in global memory) to the fused riccati_gain kernel (intermediates in shared memory) on the Jetson AGX Orin. Above one favors fusion. Color identifies the problem size,

(n_{x},n_{u})

. Solid curves are fp32 , and dashed fp64 .

GPU Acceleration

GPU acceleration uses parallel processors, specialized kernels, and memory-aware systems to speed computation across AI and scientific workloads.

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RoboGPU: Accelerating GPU Collision Detection for Robotics

Lufei Liu, Liwei Xue, Yuan Hsi Chou, Jocelyn Zhao+3

University of British Columbia Vancouver, Canada

GPU Acceleration Robotics Robot Collision Avoidance

Open paper AskPDF arXiv

Autonomous robots are anticipated to be deployed soon in domains ranging from transportation to healthcare and home assistance. Enabling autonomous robotics requires a computation platform flexible enough to execute a diverse and evolving collection of workloads while meeting real-time requirements. We believe a GPU-like architecture will be a key component of such platforms. Recent GPUs combine a flexible parallel processing fabric augmented with efficient support for important application domains via embedded accelerators (e.g., Tensor Cores), and a GPU-like architecture has reportedly been adopted for the Tesla AI5 accelerator. While current GPUs are effective at supporting emerging neural motion planners, we find that collision detection is crucial for evaluating their proposed trajectories and that this step appears to require dedicated acceleration to operate in real-time. In this work, we propose RoboCore, an accelerator block embedded within a robotics-focused GPU (RoboGPU) architecture. We explore and compare architectural modifications to address the gaps of existing ray tracing accelerators (RTAs) for robotics and find that RoboCore computes collision queries 2.8

\times

faster than RTA implementations using 48% less energy with 2% more area than RTAs. RoboCore is 13.3

\times

faster than a CUDA baseline, and achieves 3.4

\times

end-to-end speedup on a neural motion planner and 1.1

\times

speedup on Monte Carlo Localization compared to a baseline GPU. This demonstrates that a hybrid approach of embedded specialization within a flexible general-purpose GPU architecture is suitable for supporting advancements in robotics. Code available at: https://ubc-aamodt-group.github.io/robogpu/

Abstract

GPU Acceleration

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