A packet-level digital hardware twin for commissioning megahertz diagnostic edge AI and plasma control system integration in tokamaks

Semin Joung; Abhilasha Dave; Luca Scomparin; Filipp Khabanov; Zheng Yan; Benedikt Geiger; George McKee; Ryan N. Coffee

physics.plasm-phSep 27, 2026

A packet-level digital hardware twin for commissioning megahertz diagnostic edge AI and plasma control system integration in tokamaks

Authors: Semin Joung, Abhilasha Dave, Luca Scomparin, Filipp Khabanov, Zheng Yan, Benedikt Geiger, George McKee, Ryan N. Coffee, +1 more

Organizations: Department of Nuclear Engineering and Engineering Physics, University of Wisconsin–Madison, Madison, WI, USA · SLAC National Accelerator Laboratory, Menlo Park, CA, USA

Abstract

High-bandwidth plasma diagnostics increasingly provide inputs to machine learning and signal-processing algorithms intended for real-time tokamak control, but the complete path from diagnostic sampling to control-system handoff is difficult to commission because of their sampling rates. We develop a packet-level digital hardware twin for the megahertz diagnostic edge-AI architecture. The simulator represents a 64-channel, 1 MHz beam emission spectroscopy (BES) diagnostic embedded in a 96-channel dual-carrier acquisition system, two 48-channel streams with SPAD0 sample counters, 10 GbE Hardware UDP transport, packet loss and network jitter, FPGA parsing and dual-carrier alignment, causal preprocessing and edge inference, a compact Ethernet result packet, receiver-side shared state, and a 1 kHz PCS-like control cycle. Binary UDP payloads and PCAP files are generated rather than emulating transport only at the array level. With a baseline of 20 samples per packet, each carrier generates 50,000 packets s $^{-1}$ and 100 MB s $^{-1}$ of user payload. A 110 ms reference run produces 11,000 HUDP packets; an intentionally dropped 20-sample packet is detected by the sample-counter continuity logic and invalidates the two overlapping 128-sample inference windows without silent interpolation. For valid windows, the configured engineering latency model gives a median last-input-to-shared-memory latency of 91.6 us and a 99th percentile of 108.1 us. A separate operating-system loopback test sends binary FPGA-result datagrams through a UDP receiver into POSIX shared memory and preserves packet sequence and CRC for 20/20 packets. Interactive GUI interfaces expose timing, packetization, network faults, inference thresholds, and control-state inspection. The framework provides a reproducible environment for testing diagnostic-to-accelerator interfaces and fail-safe behavior for deployment on fusion devices.

Figures & tables

Figure 1: DIII-D-oriented full-system simulator. The modeled control-critical path begins with 64-channel BES, uses two 48-channel acquisition carriers with SPAD0 sample counters and 10 GbE HUDP transport, reconstructs a synchronized stream at an edge FPGA, and forwards a compact result packet through a PCS-facing receiver and shared state to a 1 kHz virtual controller. Recording and replay are parallel support paths. The architecture represents the proposed path.

Level	Examples	Treatment in the simulator
Project-grounded / vendor-documented	64 active BES channels; 96-channel planned capacity; two 48-channel carriers; 1 MSPS effective rate; HUDP transport; SPAD0 sample counter; FPGA-to-receiver-to-shared-state concept	Fixed by the baseline configuration but retained as named parameters so that the implementation can be updated with the final hardware configuration.
Configurable engineering assumptions	samples per packet, MTU, network jitter, deskew depth, causal filter band, inference latency, PCS cycle, stale timeout	User-adjustable values used for commissioning sweeps and sensitivity tests; no claim that they are measured DIII-D latencies.
Simulator-only placeholders	synthetic ELM probability model, virtual plasma/RMP response, PCS Packet v0 binary layout	Isolated behind explicit interfaces so that trained models, measured actuator behavior, and the final DIII-D PCS packet/shared-memory schema can replace them without changing the surrounding data path.

Table 1: Fidelity levels used in the digital hardware twin simulator.

Figure 2: Packet contract and fault propagation in the baseline simulation. (a) One HUDP user payload contains 20 samples, each composed of 48 16-bit ADC values and a 32-bit SPAD0 sample counter, for 2000 bytes per packet. (b) Carrier-B packet sequence 4200 is intentionally dropped. (c) The missing 20-sample interval invalidates the two 128-sample, 64-stride FPGA windows that overlap the missing counters. All results in this figure are generated by the simulator rather than measured on DIII-D hardware.

Figure 3: Configured engineering latency for valid windows. (a) Distribution of last-input-ready to shared-memory-write latency for the 110 ms baseline run. (b) Median component budget. The 1 ms line is a reference requirement, not a measured hardware comparison. All component delays in this figure are configurable simulator assumptions.

Figure 4: PCS-facing simulator behavior and process-level loopback verification. (a) Synthetic edge outputs, virtual controller request, and shared-state age in the 1 kHz PCS-like loop. Event labels and actuator response are simulator-only. (b) Generation and sequence counters observed while binary result packets cross a localhost UDP receiver and POSIX shared-memory boundary. (c) Example virtual event outcomes and CRC summary. The final state-age increase occurs after the 110 ms synthetic data stream ends and demonstrates the stale-state logic.

Figure 5: Static view of the interactive commissioning interface generated from the same synthetic HDF5 and packet traces used in the paper. The operator can inspect $P_{\mathrm{ELM}}$ , $v_{\mathrm{turb}}$ , the virtual actuator request, stream validity, latency statistics, and the spatial BES state. The current GUI is a development tool and not the production DIII-D PCS user interface.

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Benchmarking Sensor Robustness in Plasma Diagnostic Models: A Systematic Evaluation on TokaMark

Neerav Gupta

Independent Researcher

Robustness Verification Diagnosis Convolutional Neural Networks

Open paper AskPDF arXiv

Plasma diagnostic models for tokamak fusion devices are almost universally evaluated on clean, complete sensor data. In practice, fusion diagnostics fail regularly: acquisition systems start late, individual sensors die, and signal dropouts cluster precisely when a plasma disruption is approaching. We present the first systematic robustness benchmark for plasma diagnostic ML using the TokaMark dataset of 11,573 MAST shots, evaluating XGBoost, LSTM, Transformer, and the TokaMark CNN baseline across six physically-grounded failure scenarios and three imputation strategies. We introduce the Robustness Score (RS) for standardized cross-architecture comparison. Our central finding is that disruption-proximate sensor failure (corruption injected in the final window timesteps) collapses sequence model performance (LSTM +212% NRMSE) while a statistical feature model remains comparatively stable (XGBoost +37%). Forward-fill imputation eliminates nearly all degradation from random dropout for sequence models (LSTM +57% to ~0%), but offers little help when the end of the window is corrupted. Shot-level alarm evaluation using ground-truth disruption timestamps reveals that LSTM alarm detection collapses to TPR=0.00 under proximate sensor failure, while mean-fill imputation recovers it to TPR=1.00, a reversal of the pattern observed in NRMSE. Plasma current emerges as the single most critical diagnostic across all architectures (+73% to +140% upon removal). Code, data, and trained checkpoints are available at https://github.com/Neerav-Gupta/tokamark-robustness.

Abstract

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